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Electrical Engineering 2021 Paper I 50 marks Solve

Paper I — Q2

(a) Find the Thevenin's equivalent of the circuit shown in Figure 2(a) below as seen from the load impedance Z_L. Also find the…

(a)

Find the Thevenin's equivalent of the circuit shown in Figure 2(a) below as seen from the load impedance Z_L. Also find the value of Z_L for maximum power transfer. 20 marks

(b)
(i)

Compute the convolution X[n] * h[n], where X[n] = (1/2)^(-n) u[-n-2] h[n] = u[n-2].

(ii)

Consider the signal X(t) shown in Figure 2(b)(ii) below. Represent the signal X(t) in terms of rectangular pulse signal V(t) shown in the same figure. 20 marks

(c)

Consider the circuit shown in Figure 2(c) below. Let inputs A, B and C be all initially LOW. Output Y is supposed to go HIGH only when A, B and C go HIGH in a certain sequence. Determine the sequence that will make Y go HIGH. Modify this circuit to use D-Flip-flops. 10 marks

हिंदी में प्रश्न पढ़ें
(a)

चित्र 2(a) में प्रदर्शित परिपथ का, भार प्रतिबाधा Z_L से दृश्य थेवेनिन समतुल्य ज्ञात कीजिए। अधिकतम शक्ति अंतरण के लिए Z_L का मान भी ज्ञात कीजिए। (20 अंक)

(b)
(i)

संवलन (कनवोल्यूशन) X[n] * h[n] की गणना कीजिए, जहाँ X[n] = (1/2)^(-n) u[-n - 2] h[n] = u[n - 2].

(ii)

चित्र 2(b)(ii) में प्रदर्शित संकेत X(t) पर विचार कीजिए । उसी चित्र में प्रदर्शित आयताकार स्पंद संकेत V(t) के सापेक्ष संकेत X(t) का निरूपण कीजिए । (20 अंक)

(c)

चित्र 2(c) में प्रदर्शित परिपथ पर विचार कीजिए । माना कि प्रारंभ में निवेश A, B और C सभी निम्न (लो) हैं । A, B और C के किसी एक विशेष प्रक्रम में उच्च (हाई) होने पर निर्गत Y का उच्च होना अपेक्षित है । उस प्रक्रम को ज्ञात कीजिए जो Y को उच्च स्तर पर ले जाएगा । इस परिपथ को D-फ्लिप-फ्लॉपों का प्रयोग करने के लिए परिवर्तित कीजिए । (10 अंक)

Q2 of the 2021 UPSC Mains Electrical Engineering Paper I, as printed
The question as printed in the 2021 Electrical Engineering paper
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The figure this question refers to, in words

The question paper is a scan and the diagram did not survive as text. This is the figure as read from the original page — every component, value and label — so the question can be worked from the text below.

(a) A circuit diagram showing a load impedance Z_L connected to a coupled-inductor network driven by an AC voltage source:

  • Leftmost vertical branch contains an AC voltage source of 100/_0 degrees V.
  • Top branch of the left loop contains a capacitor with impedance -j2 ohms connected in series between the positive/top terminal of the AC source and the top terminal of a coupled inductor.
  • The left coupled inductor is vertical with impedance j4 ohms, having a dot at its top terminal.
  • The right coupled inductor is vertical with impedance j9 ohms, having a dot at its top terminal.
  • The two coupled inductors have a mutual coupling coefficient k = 0.5 indicated above them with a curved double-headed arrow.
  • The bottom terminals of both coupled inductors (j4 ohms and j9 ohms) meet at a common junction node.
  • From this common junction node, a vertical central branch goes down containing a series combination of a 2 ohm resistor and a j3 ohm inductor, connecting to the bottom reference rail.
  • The bottom reference rail connects the negative/bottom terminal of the voltage source, the bottom of the 2 ohm + j3 ohm branch, and the bottom terminal of the load impedance Z_L.
  • From the top terminal of the j9 ohm inductor, the top branch of the right loop continues horizontally through an inductor with impedance j2 ohms to the top terminal of the load impedance Z_L.
  • The load impedance Z_L is connected vertically across the output terminals.

(b) Figure 2(b)(ii) consists of two waveforms plotted against time t:

  1. Signal X(t): Plot of X(t) versus t. The signal is piecewise constant and zero outside [0, 4]. For 0 <= t < 1, X(t) = 1; for 1 <= t < 2, X(t) = 2; for 2 <= t < 3, X(t) = 3; for 3 <= t < 4, X(t) = 2; and X(t) = 0 for t < 0 and t > 4. Dashed vertical grid lines extend down to the t-axis at t = 1, 2, and 3. The t-axis has labeled tick marks at 0, 1, 2, 3, 4, and the vertical axis has labeled tick marks at 1, 2, 3.
  2. Signal V(t): Plot of a rectangular pulse V(t) versus t. The pulse has an amplitude of 1 spanning from t = -1 to t = 1, and is 0 elsewhere. The horizontal axis is labeled at -1 and 1, and the vertical axis is labeled at 1.

(c) A digital circuit schematic titled 'Figure 2(c)' consisting of two JK flip-flops:

  1. First flip-flop (left):
  • J input is connected to input terminal A.
  • Clock (CLK) input is connected to input terminal B.
  • K input is connected to ground.
  • Active-low clear input (CLR with an inversion bubble) is connected to an active-low signal line labeled 'Start' (indicated with a negative pulse icon).
  • Output Q is labeled X.
  1. Second flip-flop (right):
  • J input is connected directly to the output X of the first flip-flop.
  • Clock (CLK) input is connected to input terminal C.
  • K input is connected to ground.
  • Active-low clear input (CLR with an inversion bubble) is connected to the same 'Start' signal line as the first flip-flop.
  • Output Q is labeled Y.

Model answer

Drafted with AI by UPSC Answer Check against this question's marking rubric, to the expected length. UPSC does not publish answers for Mains — this is one way to score well, not an official key. How we build rubrics and answers.

(a) Thevenin equivalent and Z_L for maximum power transfer Mutual reactance: ωM = k√(4 × 9) = 0.5 × 6 = 3, so jωM = j3 Ω. Both coils have their dots at the top, and the current entering each dot is taken as I₁ (primary) and I₂ (secondary, flowing through Z_L and the series j2 Ω). The (2 + j3) Ω branch carries I₁ + I₂. V_th: with Z_L open, I₂ = 0 and I₁ = 100/(−j2 + j4 + 2 + j3) = 100/(2 + j5). The open-circuit voltage is the drop in the common (2 + j3) branch plus the voltage induced in the j9 coil by I₁: V_th = I₁(2 + j3) + j3 I₁ = I₁(2 + j6) = 100(2 + j6)/(2 + j5) = (3400 + j200)/29 ≈ 117.2 + j6.9 V ≈ 117.4∠3.4° V. Z_th: short the source (I₁ = −(2 + j6)I₂/(2 + j5) from the primary mesh) and use the secondary mesh (2 + j14 + Z_L) I₂ + (2 + j6) I₁ = 0: Z_th = (2 + j14) − (2 + j6)²/(2 + j5) = (2 + j14) − (56 + j208)/29 = (2 + j198)/29 ≈ 0.069 + j6.83 Ω. Maximum power transfer: Z_L = Z_th* ≈ 0.069 − j6.83 Ω (a resistor of 0.069 Ω in series with a capacitive reactance of 6.83 Ω). With 100 V taken as rms, P_max = |V_th|²/(4R_th) ≈ 5 × 10⁴ W.

**(b)(i) Convolution X[n] * h[n] X[n] = (1/2)⁻ⁿ u[−n − 2] = 2ⁿ u[−n − 2], non-zero for n ≤ −2; h[n] = u[n − 2], non-zero for n ≥ 2. y[n] = Σₖ 2ᵏ u[−k − 2] u[n − k − 2], with k ≤ −2 and k ≤ n − 2, so k ≤ M = min(−2, n − 2). Σₖ₌₋∞^M 2ᵏ = 2^(M+1). For n ≤ 0, M = n − 2 and y[n] = 2^(n−1). For n ≥ 0, M = −2 and y[n] = 1/2. y[n] = 2^(n−1) for n ≤ 0 and 1/2 for n ≥ 0** (both give 1/2 at n = 0): a left-sided exponential that flattens to 0.5.

(b)(ii) X(t) in terms of V(t) V(t) is a unit pulse on −1 ≤ t ≤ 1, so V(t − t₀) is a unit pulse on [t₀ − 1, t₀ + 1]. X(t) is 1 on [0, 1], 2 on [1, 2], 3 on [2, 3] and 2 on [3, 4]. Try V(t − 1) + V(t − 2) + 2V(t − 3): on [0, 1] the sum is 1; on [1, 2] it is 1 + 1 = 2; on [2, 3] it is 1 + 2 = 3; on [3, 4] it is 2. X(t) = V(t − 1) + V(t − 2) + 2V(t − 3).

(c) Sequence for Y HIGH and the D flip-flop version K = 0 on both stages, so each JK stage obeys Q⁺ = J + Q: it sets on a clock edge only if J is HIGH. Stage 1 has J = A and clock B, so X goes HIGH on the rising edge of B only if A is already HIGH. Stage 2 has J = X and clock C, so Y goes HIGH on the rising edge of C only if X is already HIGH. From all-LOW (cleared by the Start pulse), the only sequence that raises Y is A, then B, then C. For D flip-flops, D = JQ̄ + K̄Q, which with K = 0 reduces to D = J + Q. So D_X = A + X clocked by B, and D_Y = X + Y clocked by C, both with the active-low clear tied to Start.

How this answer will be evaluated

What earns full marks: Complete working with correct equivalent circuits, accurate calculations, and clear diagrams for all parts

Evaluation rubric

Each sub-part is marked on its own, against the marks and word limit printed on the paper.

  1. (a) Thevenin equivalent seen by Z_L in the coupled circuit and the Z_L for maximum power transfer. 20 marks

    calculate— given → formula → substitution → result with units → interpretation

    Must cover

    • Handle the coupling correctly: jωM = j3 Ω, dots at the top, (2 + j3) Ω branch carrying I₁ + I₂.
    • Obtain V_th = 100(2 + j6)/(2 + j5) ≈ 117.4∠3.4° V and Z_th = (2 + j198)/29 ≈ 0.069 + j6.83 Ω.
    • State Z_L = Z_th* ≈ 0.069 − j6.83 Ω for maximum power transfer.

    Loses marks

    • Sign errors in the mutual-inductance terms.
    • Final impedances without units or without the equivalent circuit.

    Earns more

    • Correct mesh equations with the mutual term.
    • Clear statement of reference polarities and current directions.

    Extra mark

    • P_max = |V_th|²/(4R_th) ≈ 5 × 10⁴ W for 100 V rms.
  2. (b) Convolution of X[n] and h[n], and X(t) in terms of the rectangular pulse V(t). 20 marks

    calculate— given → formula → substitution → result with units → interpretation

    Must cover

    • Write the convolution sum with limits k ≤ min(−2, n − 2) and sum the geometric series to get y[n] = 2^(n−1) for n ≤ 0 and 1/2 for n ≥ 0.
    • Handle the step functions u[−n − 2] and u[n − 2] correctly.
    • Give X(t) = V(t − 1) + V(t − 2) + 2V(t − 3) with the shifts and amplitudes checked interval by interval.

    Loses marks

    • Wrong limits from the unit steps.
    • Missing time shifts or amplitude 2 in the pulse representation.

    Earns more

    • Step-by-step convolution shown.
    • Pulse boundaries identified clearly.

    Extra mark

    • Z-transform check of the convolution result.
  3. (c) Input sequence that makes Y HIGH and the D flip-flop version of the circuit. 10 marks

    describe— define → structure or process in order → labelled diagram → significance

    Must cover

    • Show Q⁺ = J + Q for each JK stage with K = 0 and deduce the sequence A, then B, then C.
    • Convert using D = JQ̄ + K̄Q = J + Q.
    • Give D_X = A + X clocked by B and D_Y = X + Y clocked by C, with the clear tied to Start.

    Loses marks

    • A wrong sequence such as C first.
    • No conversion formula or an incomplete circuit.

    Earns more

    • Correct reasoning on clock and J inputs of each stage.
    • D inputs labelled correctly.

    Extra mark

    • Timing diagram of A, B, C, X and Y.
What "Solve" is asking you to do

Choose the method, then carry it through to a final answer. Identifying what kind of problem this is and why that method applies is the first thing marked; a correct figure arrived at invisibly earns almost nothing.

Structure that answers it

Given data and what is required → method chosen, with the reason it applies → set-up (equation, circuit, free body, trial balance) → working, step by step → answer with units and any condition of validity

Where marks are lost

Doing the middle steps mentally and writing only the result. In mathematics papers, a further loss comes from giving a decimal where the exact value in surds or fractions was wanted, or from skipping the justification a part explicitly asks for.

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