(a) Find the Thevenin's equivalent of the circuit shown in Figure 2(a) below as seen from the load impedance Z_L. Also find the value of Z_L for maximum power transfer. (20 marks)

(b) (i) Compute the convolution X[n] * h[n], where
X[n] = (1/2)^(-n)

Question

(a) Find the Thevenin's equivalent of the circuit shown in Figure 2(a) below as seen from the load impedance Z_L. Also find the value of Z_L for maximum power transfer. (20 marks)

(b) (i) Compute the convolution X[n] * h[n], where
X[n] = (1/2)^(-n) u[-n-2]
h[n] = u[n-2].

(ii) Consider the signal X(t) shown in Figure 2(b)(ii) below. Represent the signal X(t) in terms of rectangular pulse signal V(t) shown in the same figure. (20 marks)

(c) Consider the circuit shown in Figure 2(c) below. Let inputs A, B and C be all initially LOW. Output Y is supposed to go HIGH only when A, B and C go HIGH in a certain sequence. Determine the sequence that will make Y go HIGH. Modify this circuit to use D-Flip-flops. (10 marks)

UPSC Answer Check · Accepted Answer

Solve this multi-part numerical problem by allocating approximately 40% time to part (a) Thevenin's equivalent and maximum power transfer, 40% to part (b) convolution and signal representation, and 20% to part (c) sequential circuit analysis and D-flip-flop modification. Begin each sub-part with the relevant circuit diagram or signal sketch, show all mathematical steps clearly, and conclude with the final numerical answer or circuit modification. For part (b)(i), carefully handle the time-reversed nature of x[n] and the shifted unit step functions.
- Part (a): Correct calculation of Thevenin's equivalent voltage (V_th) by open-circuit analysis and Thevenin's equivalent impedance (Z_th) by deactivating independent sources
- Part (a): Application of maximum power transfer theorem stating Z_L = Z_th* (complex conjugate) for AC circuits, or Z_L = Z_th for purely resistive circuits
- Part (b)(i): Proper handling of convolution with anti-causal signal x[n]=(1/2)^(-n)u[-n-2] rewritten as 2^n u[-n-2], correct determination of overlap regions for n<0 and n≥0
- Part (b)(ii): Expression of x(t) as weighted sum of shifted rectangular pulses V(t), identification of amplitude and time-shift parameters from figure
- Part (c): Analysis of sequential circuit to determine required input sequence (likely A→B→C or specific order) that activates Y through state transitions
- Part (c): Correct modification to D-flip-flops: converting existing flip-flops or designing equivalent state machine with proper excitation table and next-state logic

Dimension	Weight	Max marks	Excellent	Average	Poor
Concept correctness	22%	11	Correctly applies Thevenin's theorem with proper source transformation, recognizes x[n] as anti-causal requiring time-reversal handling in convolution, and accurately identifies sequence detector operation with proper state machine concepts for D-flip-flop conversion	Applies Thevenin's theorem with minor errors in source deactivation, attempts convolution but mishandles unit step boundaries or signal regions, identifies partial sequence or makes errors in flip-flop excitation table	Confuses Thevenin's with Norton's theorem, completely mishandles anti-causal convolution or uses wrong formula, fails to recognize sequential nature or makes fundamental errors in flip-flop conversion
Numerical accuracy	22%	11	Computes exact V_th, Z_th and optimal Z_L values; derives closed-form convolution result with correct summation limits and final expression; determines precise sequence A-B-C or equivalent with correct state encoding	Correct method but arithmetic errors in complex impedance calculation, convolution limits or summation; partial sequence identification with one state transition error, minor errors in D-flip-flop characteristic equation	Major calculation errors in Thevenin's parameters, completely wrong convolution result or missing regions, incorrect sequence or no numerical working for flip-flop modification
Diagram quality	16%	8	Clear original circuit with load terminals marked for Thevenin's, neat Thevenin's equivalent circuit with V_th and Z_th labeled; proper sketches of x[n], h[n] and their flipped/shifted versions for convolution; original and modified sequential circuits with state transitions clearly shown	Acceptable circuit diagrams missing some labels, basic signal sketches without proper annotation, sequential circuit drawn but flip-flop connections unclear	Missing or unrecognizable diagrams, no visualization of convolution overlap regions, no circuit modification shown or completely wrong flip-flop symbols
Step-by-step derivation	22%	11	Systematic nodal/mesh analysis for V_th, clear impedance combination for Z_th; explicit convolution integral/sum with case analysis for different n ranges; complete state table, excitation table and Boolean minimization for D-flip-flop implementation	Some steps skipped in Thevenin's derivation, convolution shown but cases merged confusingly, state analysis present but excitation table incomplete or logic minimization missing	No derivation shown—only final answers, convolution written as single expression without case analysis, no state transition analysis or arbitrary flip-flop connections without justification
Practical interpretation	18%	9	Explains significance of maximum power transfer in transmission systems (e.g., antenna matching); discusses practical implications of anti-causal systems and realizability; relates sequence detector to industrial control applications (e.g., safety interlocks, password verification) and explains advantage of D-flip-flops over other types	Brief mention of power transfer importance, limited discussion on causality, generic statement about sequence detectors without application context	No physical interpretation provided, treats problem as purely mathematical exercise, no discussion of why D-flip-flops are preferred or their practical advantages in synchronous design

Q2

Directive word: Solve

How this answer will be evaluated

Approach

Key points expected

Evaluation rubric

Practice this exact question

More from Electrical Engineering 2021 Paper I