(a) Consider a discrete time system with transfer function given by H(z) = Y(z)/R(z) = (z⁻¹ - ½z⁻²)/(1 - z⁻¹ + 2/9…

(a) Responses of the discrete-time system Difference equation: y[n] = y[n−1] − (2/9)y[n−2] + r[n−1] − ½r[n−2]. Poles: H(z) = (z − ½)/[(z − ⅓)(z − ⅔)], both inside the unit circle, so the system is stable. (i) Impulse response (R = 1). H(z) = ½/(z − ⅓) + ½/(z − ⅔) = ½z⁻¹/(1 − ⅓z⁻¹) + ½z⁻¹/(1 − ⅔z⁻¹), so h[n] = ½[(1/3)ⁿ⁻¹ + (2/3)ⁿ⁻¹] u[n − 1]; h = 0, 1, ½, 5/18, … (matches the recursion). (ii) Step response, zero initial conditions (R = z/(z − 1)). Y/z = (z − ½)/[(z − ⅓)(z − ⅔)(z − 1)] has residues 9/4 at z = 1, −3/4 at ⅓ and −3/2 at ⅔: y[n] = [9/4 − (3/4)(1/3)ⁿ − (3/2)(2/3)ⁿ] u[n]; y = 0, 1, 3/2, …, and y(∞) = H(1) = 9/4. (iii) With y[−1] = 1, y[−2] = 2. The input is causal. The one-sided transform gives Y(1 − z⁻¹ + (2/9)z⁻²) = (z⁻¹ − ½z⁻²)R + [y[−1] − (2/9)y[−2]] − (2/9)y[−1]z⁻¹ = (z⁻¹ − ½z⁻²)R + 5/9 − (2/9)z⁻¹. The zero-input part has residues 1/9 at ⅓ and 4/9 at ⅔: y_zi[n] = (1/9)(1/3)ⁿ + (4/9)(2/3)ⁿ. Adding the zero-state part, y[n] = 9/4 − (23/36)(1/3)ⁿ − (19/18)(2/3)ⁿ, n ≥ 0; y[0] = 5/9 and y[1] = 4/3, as the recursion gives.

(b)(i) Verification of Figure 4(b) Each 2-to-1 MUX has select S₀: M₀ = S₀′D₀ + S₀D₁, M₁ = S₀′D₂ + S₀D₃, M₂ = S₀′D₄ + S₀D₅, M₃ = S₀′D₆ + S₀D₇. They feed inputs 00, 01, 10, 11 of the 4-to-1 MUX with selects S₂ (MSB) and S₁: Y = S₂′S₁′M₀ + S₂′S₁M₁ + S₂S₁′M₂ + S₂S₁M₃ Y = S₂′S₁′S₀′D₀ + S₂′S₁′S₀D₁ + S₂′S₁S₀′D₂ + S₂′S₁S₀D₃ + S₂S₁′S₀′D₄ + S₂S₁′S₀D₅ + S₂S₁S₀′D₆ + S₂S₁S₀D₇ Truth table (S₂S₁S₀ → Y): 000 → D₀, 001 → D₁, 010 → D₂, 011 → D₃, 100 → D₄, 101 → D₅, 110 → D₆, 111 → D₇. This is an 8-to-1 multiplexer.

(b)(ii) F(A, B, C, D, E) with an 8-to-1 MUX The printed list is read as minterms 0, 1, 2, 4, 5, 6, 7, 13, 14 and every minterm from 20 to 31. Use A, B, C as selects S₂S₁S₀; each data input is a function of D and E over minterms 4i to 4i + 3: I₀ (m0–3: 0, 1, 2 present) = D′ + E′ = (DE)′; I₁ (m4–7) = 1; I₂ (m8–11) = 0; I₃ (m12–15: m13 and m14 present) = D ⊕ E; I₄ (m16–19) = 0; I₅, I₆, I₇ (m20–31) = 1. So one 8-to-1 MUX, one NAND gate (inputs D, E) and one XOR gate (inputs D, E) realise F.

(c) Gain of the T-network inverting amplifier With A₀ = ∞ the inverting node is a virtual ground, so i = V_in/R₂ flows through R₃ and V_x = −iR₃. KCL at V_x: i = V_x/R₄ + (V_x − V_out)/R₁, so V_out = V_x(1 + R₁/R₄) − R₁i. V_out/V_in = −(R₁ + R₃ + R₁R₃/R₄)/R₂ The R₁R₃/R₄ term gives high gain without very large resistors. R₁ → 0: gain → −R₃/R₂; V_x is tied to the output, so R₄ only loads the output and the circuit is a plain inverting amplifier with R₃ as feedback. R₃ → 0: gain → −R₁/R₂; V_x sits at virtual ground, R₄ carries no current, and R₁ is the feedback resistor. In both limits the multiplying action of the T-network disappears.