(a) Consider a discrete time system with transfer function given by

H(z) = Y(z)/R(z) = (z⁻¹ - ½z⁻²)/(1 - z⁻¹ + 2/9 z⁻²).

Calculate the following :

(i) The impulse response of the system

(ii) The step response of the system with zero initial condi

Question

(a) Consider a discrete time system with transfer function given by

H(z) = Y(z)/R(z) = (z⁻¹ - ½z⁻²)/(1 - z⁻¹ + 2/9 z⁻²).

Calculate the following :

(i) The impulse response of the system

(ii) The step response of the system with zero initial conditions

(iii) The step response of the system with initial conditions y[-1] = 1 and y[-2] = 2 20

(b) (i) Verify by determining the logic equation for the output and by constructing the truth table for the logic circuit shown in Figure 4(b).

(ii) Use an 8 to 1 multiplexer and logic gates to implement the following function :

F(A, B, C, D, E) = Σ m (0, 1, 2, 4, 5, 6, 7, 13, 14, 20, 21, ..., 28, 29, 30, 31)

20

Figure 4(b)

(c) Determine the closed loop gain of the inverting amplifier shown in Figure 4(c) below. Explain the result if R₁ → 0 or R₃ → 0.

10

UPSC Answer Check · Accepted Answer

Calculate the required responses and circuit parameters systematically. For part (a) [20 marks], perform partial fraction expansion on H(z) and apply Z-transform properties for impulse and step responses, handling initial conditions via unilateral Z-transform. For part (b) [20 marks], derive the logic equation from Figure 4(b), construct truth table, then implement F(A,B,C,D,E) using 8:1 MUX with A,B,C as select lines. For part (c) [10 marks], apply ideal op-amp assumptions to find closed-loop gain and analyze limiting cases. Allocate approximately 40% time to (a), 35% to (b), and 25% to (c).
- Part (a)(i): Factor denominator, perform partial fraction expansion, identify poles at z=1/3 and z=2/3, obtain h[n] = [3(1/3)^n - 3(2/3)^n]u[n-1] or equivalent causal form
- Part (a)(ii): Apply step input R(z)=z/(z-1), use final value theorem or convolution sum, obtain y_step[n] with zero initial conditions
- Part (a)(iii): Apply unilateral Z-transform accounting for y[-1]=1, y[-2]=2, separate zero-state and zero-input responses, combine for total response
- Part (b)(i): Derive Boolean expression from Figure 4(b) circuit topology, verify with complete truth table showing all input combinations and output
- Part (b)(ii): Implement 5-variable function using 8:1 MUX with A,B,C as select inputs, determine D,E combinations for each minterm group (0-7, 13-14, 20-21, 28-31), connect appropriate logic to data inputs
- Part (c): Apply virtual ground concept, derive V_o/V_i = -R_f/R_1 where R_f involves R_2,R_3 network, analyze R_1→0 (infinite gain/saturation) and R_3→0 (gain becomes -R_2/R_1) cases with practical implications

Dimension	Weight	Max marks	Excellent	Average	Poor
Concept correctness	20%	10	Correctly applies Z-transform properties including region of convergence, unilateral vs bilateral transforms for initial conditions; proper Boolean algebra and MUX implementation theory; correct op-amp virtual short and virtual ground concepts	Minor errors in transform pairs or initial condition handling; partially correct logic simplification; basic op-amp assumptions applied with some confusion	Fundamental misunderstanding of Z-transform convergence, causal systems, or pole-zero analysis; incorrect MUX select line assignment; wrong op-amp gain formula
Numerical accuracy	20%	10	Accurate partial fraction coefficients (3, -3), correct pole locations (1/3, 2/3), precise arithmetic in step response coefficients, correct minterm identification for 5-variable function, accurate gain expression	Minor arithmetic errors in coefficients, one incorrect pole location, small errors in minterm expansion, algebraic slips in final gain expression	Major calculation errors leading to wrong impulse response, incorrect pole identification, wrong minterm count or values, fundamentally incorrect gain formula
Diagram quality	15%	7.5	Clear pole-zero plot for H(z) with ROC indicated; neat truth table with proper alignment; well-labeled 8:1 MUX implementation diagram showing select lines, data inputs with logic gates; clean op-amp circuit with clear node labels	Basic diagrams present but poorly labeled or missing some annotations; truth table readable but formatting inconsistent; MUX diagram missing some connections	Missing essential diagrams, illegible sketches, no circuit diagram for part (c), or completely wrong figure interpretations
Step-by-step derivation	25%	12.5	Complete partial fraction expansion shown with residue calculation; clear separation of zero-state and zero-input responses; systematic truth table construction; explicit MUX input derivation from minterm groups; detailed nodal analysis for op-amp circuit	Some steps skipped or condensed; missing intermediate algebraic steps; truth table presented without derivation; MUX inputs stated without justification; brief nodal analysis	No derivation shown, only final answers; jumps from transfer function to response without method; truth table asserted without construction; no explanation of MUX implementation strategy
Practical interpretation	20%	10	Discusses stability (poles inside unit circle), transient vs steady-state in step response; explains why R_1→0 causes op-amp saturation (practical limitation) and R_3→0 reduces to standard inverting amplifier; relates MUX implementation to digital system design constraints	Brief mention of stability or convergence; superficial comment on limiting cases without physical explanation; minimal practical context	No interpretation of results, purely mathematical treatment; fails to recognize physical implications of parameter limits; no system-level insight

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