(a)(i) Prove that the minimum distance of any linear (n, k) block code satisfies dmin ≤ 1 + n – k. (5 marks)

(a)(ii) Show that the minimum Hamming distance of a linear block code is equal to the minimum number of columns of its parity check matrix t

Question

(a)(i) Prove that the minimum distance of any linear (n, k) block code satisfies dmin ≤ 1 + n – k. (5 marks)

(a)(ii) Show that the minimum Hamming distance of a linear block code is equal to the minimum number of columns of its parity check matrix that are linearly dependent. From this conclude that the minimum Hamming distance of a Hamming code is always equal to 3. (15 marks)

(b) A commercial interface unit uses different names for the handshake lines associated with the transfer of data from the I/O device into the interface unit. The interface input handshake line is labelled STB (strobe), and the interface output handshake line is labelled IBF (input buffer full). A low-level signal on STB loads data from the I/O bus into the interface data register. A high-level signal on IBF indicates that the data item has been accepted by the interface. IBF goes low after an I/O read signal from the CPU when it reads the content of the data register.

(i) Draw the block diagram showing the CPU, the interface, and the I/O device together with the pertinent interconnections among the three units.

(ii) Draw a timing diagram for the handshaking transfer.

(iii) Obtain a sequence of events flowchart for the transfer from the device to the interface and from the interface to the CPU. (20 marks)

(c) For a 3-bus power system, assume

Voltage at bus – 1 : V₁ = (1·05 + j 0) pu,

Voltage at bus – 2 : V₂ = (0·9812 – j 0·0522) pu and

Voltage at bus – 3 : V₃ = (0·999 – j 0·0468) pu.

The line impedances are shown below :

Bus code Impedances (in p.u.)

1 – 2 (0·02 + j 0·04)

1 – 3 (0·01 + j 0·03)

2 – 3 (0·0125 + j 0·025)

Compute Real and Reactive power loss in all the lines and also compute total system loss. (10 marks)

UPSC Answer Check · Accepted Answer

Begin with rigorous mathematical proofs for (a)(i)-(ii) establishing the Singleton bound and Hamming code properties using parity check matrix concepts. For (b), construct clear block diagrams, timing diagrams, and flowcharts showing the STB-IBF handshake protocol between CPU, interface, and I/O device. Conclude with systematic power flow calculations for (c), computing complex power injections and line losses using the given 3-bus voltages and impedances. Allocate approximately 40% time to part (a), 40% to part (b), and 20% to part (c) based on mark distribution.
- Proof of Singleton bound dmin ≤ 1 + n – k using linear code properties and dimension arguments
- Demonstration that dmin equals minimum number of linearly dependent columns in parity check matrix H
- Conclusion that Hamming codes have dmin = 3 based on H having distinct non-zero columns
- Block diagram showing CPU, interface unit, and I/O device with STB, IBF, data bus, and control signal interconnections
- Timing diagram with correct sequence: STB low → data loaded → IBF high → CPU read → IBF low
- Flowchart distinguishing device-to-interface transfer (STB-driven) from interface-to-CPU transfer (read-driven)
- Calculation of line currents using Iij = (Vi - Vj)/Zij for all three lines in the power system
- Computation of complex power loss Sloss = |Iij|² × Zij and separation into real (P) and reactive (Q) components for each line

Dimension	Weight	Max marks	Excellent	Average	Poor
Concept correctness	20%	10	Correctly applies coding theory concepts (Singleton bound, parity check matrix rank, Hamming code construction), accurately describes asynchronous handshaking protocols, and properly uses power system analysis fundamentals (per-unit system, complex power flow); no conceptual errors in any sub-part	Generally correct concepts with minor errors in one sub-part, such as incomplete proof justification or slightly mischaracterized handshake timing relationships	Fundamental misconceptions evident, such as confusing minimum distance with code rate, misunderstanding STB/IBF signal directions, or incorrect power flow equation application
Numerical accuracy	15%	7.5	Precise calculations for part (c): correct complex arithmetic for line currents, accurate \|I\|²Z computations, proper separation of real and reactive losses, and correct total system loss summation with appropriate significant figures	Correct methodology with minor arithmetic errors or sign mistakes in complex number operations, leading to partially correct final values	Major calculation errors, incorrect formula application (e.g., using voltage magnitude instead of phasor difference), or missing numerical work for line losses
Diagram quality	20%	10	Clear, labeled block diagram with all three units and signal directions; precise timing diagram showing STB pulse, data valid period, IBF assertion, and CPU read timing; systematic flowchart with decision diamonds and process boxes for both transfer phases	Generally understandable diagrams with minor labeling omissions or timing sequence ambiguities, or flowchart missing some decision points	Missing or seriously flawed diagrams, incorrect signal directions, timing violations (e.g., IBF going low before CPU read), or unstructured flowcharts
Step-by-step derivation	25%	12.5	Rigorous proof structure for (a)(i) showing dmin ≤ n-k+1 via generator matrix row reduction; complete derivation connecting linear dependence of H columns to non-zero codeword weight; systematic power flow derivation showing current, power injection, and loss calculations with clear intermediate steps	Correct overall approach with gaps in logical rigor, such as asserting without proving the column dependence property, or skipping intermediate steps in power calculations	Missing proofs, circular reasoning, or purely numerical approach without theoretical foundation; no derivation shown for key results
Practical interpretation	20%	10	Explains practical significance: Singleton bound as fundamental limit on error correction capability, Hamming code's single-error correction in communication systems, handshake protocol ensuring reliable data transfer in microprocessor systems like 8085/8086, and line loss computation relevance for Indian power grid efficiency analysis	Brief mention of practical relevance without elaboration, or generic statements not tied to specific applications in the three topic areas	No practical context provided; purely theoretical treatment without connecting to real-world coding applications, computer interfacing standards, or power system operations

Q8

Directive word: Prove

How this answer will be evaluated

Approach

Key points expected

Evaluation rubric

Practice this exact question

More from Electrical Engineering 2021 Paper II