(a)(i) Prove that the minimum distance of any linear (n, k) block code satisfies dmin ≤ 1 + n – k. (5 marks) (a)(ii) Show that…

(a)(i) Let H be the (n−k)×n parity-check matrix of the (n,k) code. Its rank is at most n−k, so any n−k+1 columns of H are linearly dependent. Hence some nonzero c with at most n−k+1 nonzero entries satisfies Σcᵢhᵢ = Hcᵀ = 0. Such a c is a nonzero codeword of weight ≤ n−k+1. Since dmin is the least nonzero weight, dmin ≤ n−k+1 = 1+n−k. Equality defines MDS codes.

(a)(ii) A vector c is a codeword iff Hcᵀ = Σcᵢhᵢ = 0. The nonzero positions of a codeword of weight w therefore index w linearly dependent columns of H, so the least number s of dependent columns satisfies s ≤ dmin. Conversely, take a minimal dependent set of s columns with Σαⱼhⱼ = 0 over that set; minimality makes every αⱼ nonzero. Put cⱼ = αⱼ on those positions and 0 elsewhere. This is a nonzero codeword of weight s, so dmin ≤ s. Hence dmin = s.

For a binary Hamming code (n = 2ᵐ−1, m ≥ 2), the columns of H are all the nonzero m-tuples, each once. No column is zero, so no single column is dependent. Over GF(2) two columns are dependent only if equal, and all are distinct, so no two are dependent. For any two columns a and b, a+b is nonzero and differs from both, so it is also a column; thus a, b and a+b are three dependent columns. Therefore s = 3 and dmin = 3.

(b)(i) Block diagram. The I/O device and the interface are joined by the I/O data bus and two handshake lines: STB (device to interface, active low) and IBF (interface to device, active high). The interface holds a data register and the IBF flag. The interface connects to the CPU through the data bus, the address-decode line and the I/O read (RD) control line; IBF can also reach the CPU as a status bit or interrupt request.

(b)(ii) Timing diagram. The waveforms run in this order: data becomes valid on the I/O bus; STB falls low, and the low level loads the data into the interface register; IBF rises high soon after, showing that the item is accepted and the device must not send another; STB returns high and the device may remove the data; the CPU asserts RD, the register contents go to the CPU data bus; IBF falls low after the read, so the interface is ready for the next item.

(b)(iii) Flowchart. Device to interface: the device waits until IBF = 0, places data on the bus and makes STB = 0. The interface loads its register and sets IBF = 1. The device sees IBF = 1, makes STB = 1 and removes the data. Interface to CPU: the CPU polls IBF (or takes an interrupt); if IBF = 1 it issues RD; the interface puts the register on the CPU bus; after the read it clears IBF = 0, and the cycle repeats.

(c) Line current Iᵢⱼ = (Vᵢ−Vⱼ)/Zᵢⱼ; loss = |Iᵢⱼ|²Zᵢⱼ = Pᵢⱼ + jQᵢⱼ. Line shunt elements are neglected.

Line 1–2: V₁−V₂ = 0.0688 + j0.0522, |ΔV|² = 0.007458, |Z|² = 0.0020, |I|² = 3.7291. P = 3.7291×0.02 = 0.07458 pu; Q = 3.7291×0.04 = 0.14917 pu.

Line 1–3: V₁−V₃ = 0.051 + j0.0468, |ΔV|² = 0.004791, |Z|² = 0.0010, |I|² = 4.7912. P = 0.04791 pu; Q = 0.14374 pu.

Line 2–3: V₂−V₃ = −0.0178 − j0.0054, |ΔV|² = 0.000346, |Z|² = 0.00078125, |I|² = 0.44288. P = 0.005536 pu; Q = 0.011072 pu.

Total loss: P = 0.07458 + 0.04791 + 0.00554 = 0.1280 pu; Q = 0.14917 + 0.14374 + 0.01107 = 0.3040 pu. Total system loss = 0.1280 + j0.3040 pu.