(a) For the circuit shown in the figure, obtain the value of voltage across 0·5 Ω and 2·5 Ω resistors using nodal current analysis. (20 marks)

(b) A causal discrete-time LTI system is described by : y[n] − (3/4)y[n−1] + (1/8)y[n−2] = x[n], where x[n

Question

(a) For the circuit shown in the figure, obtain the value of voltage across 0·5 Ω and 2·5 Ω resistors using nodal current analysis. (20 marks)

(b) A causal discrete-time LTI system is described by : y[n] − (3/4)y[n−1] + (1/8)y[n−2] = x[n], where x[n] and y[n] are the input and output of the system respectively. (i) Determine the system transfer function H(z). (ii) Find the impulse response h[n] of the system. (iii) Find the step response s[n] of the system. (20 marks)

(c) Consider the figure of differential pair given below. Neglecting the early effect, determine the change in V_X, V_Y, V_X - V_Y if (i) V_CC rises by ΔV and R_C1 = R_C2 = R_C. (ii) I_EE experiences a change of ΔI and R_C1 = R_C2 = R_C. (iii) R_C1 = R_C2 + ΔR. (10 marks)

UPSC Answer Check · Accepted Answer

Solve this multi-part numerical problem by allocating approximately 40% time to part (a) nodal analysis, 40% to part (b) DSP system analysis, and 20% to part (c) differential pair sensitivity analysis. Begin each part with clear circuit/system identification, show complete mathematical working with proper notation, and conclude with verified numerical answers. For (b), explicitly state ROC for causality; for (c), use small-signal approximation and symmetry arguments.
- Part (a): Correct identification of reference node and formulation of nodal equations using KCL; proper handling of conductances and current sources in the network
- Part (a): Accurate solution of simultaneous equations yielding specific voltage values across 0.5 Ω and 2.5 Ω resistors with proper units
- Part (b)(i): Derivation of H(z) = 1/(1 - 0.75z⁻¹ + 0.125z⁻²) with correct ROC |z| > 0.5 for causal system; proper factorization of denominator
- Part (b)(ii): Partial fraction expansion and inversion to obtain h[n] = [2(0.5)ⁿ - (0.25)ⁿ]u[n] showing recognition of distinct real poles at 0.5 and 0.25
- Part (b)(iii): Convolution of h[n] with unit step or multiplication by z/(z-1) in z-domain to derive s[n] = [4 - 4(0.5)ⁿ + (0.25)ⁿ/3]u[n] with steady-state value 8/3
- Part (c): Application of half-circuit concept and symmetry; for (i) ΔV_X = ΔV_Y = ΔV (common-mode), for (ii) ΔV_X = -ΔV_Y = -ΔI·R_C/2 (differential), for (iii) Δ(V_X-V_Y) = -I_EE·ΔR/2 showing CMRR degradation

Dimension	Weight	Max marks	Excellent	Average	Poor
Concept correctness	20%	10	Correctly applies KCL for nodal analysis in (a), recognizes LTI system properties and causality constraints in (b), and uses differential pair symmetry with proper common-mode/differential-mode distinction in (c); no conceptual errors in any sub-part	Minor errors in applying nodal analysis or partial fraction expansion; some confusion between causal and non-causal systems or ROC specification; incomplete understanding of differential pair operating regions	Fundamental misunderstanding of nodal analysis, treats system as non-causal or misses ROC entirely, or fails to recognize differential pair symmetry and small-signal conditions
Numerical accuracy	20%	10	All final numerical values correct: voltages in (a), H(z) coefficients and closed-form h[n], s[n] expressions in (b), and sensitivity expressions in (c); proper handling of fractions and decimal conversions	Correct approach but arithmetic errors in solving simultaneous equations, partial fraction coefficients, or final algebraic simplification; one sub-part with significant calculation error	Multiple numerical errors across sub-parts; incorrect pole locations in (b), wrong steady-state values, or sign errors in differential pair analysis rendering answers physically meaningless
Diagram quality	15%	7.5	Clear redrawn circuit for (a) with nodes labeled and reference indicated; pole-zero plot for (b) showing poles at 0.25 and 0.5 with unit circle and ROC shaded; differential pair schematic for (c) with V_X, V_Y, I_EE clearly marked	Diagrams present but missing key labels, unclear node numbering, or hand-drawn sketches without proper scaling; pole-zero plot without explicit ROC indication	Missing diagrams despite question referring to figures; illegible sketches; or completely misdrawn circuits showing wrong topology
Step-by-step derivation	25%	12.5	Complete logical flow: KCL equations → matrix form → solution for (a); Z-transform → algebraic manipulation → partial fractions → inversion for (b); small-signal model → symmetry analysis → incremental changes for (c); each step justified	Some steps skipped or combined without clarity; missing intermediate algebraic steps making verification difficult; jumps from H(z) to h[n] without showing partial fractions	Disorganized presentation with no logical sequence; final answers stated without derivation; or incorrect methods leading to coincidentally correct answers without valid reasoning
Practical interpretation	20%	10	Interprets (a) results in terms of power dissipation and voltage division; discusses (b) system stability (BIBO stable, poles inside unit circle), time constant, and settling behavior; explains (c) results as common-mode rejection and power supply rejection ratio (PSRR) in analog IC design relevant to Indian semiconductor initiatives	Brief mention of stability or CMRR without elaboration; generic statements about system behavior without linking to specific numerical results	No physical interpretation provided; fails to recognize that (c) analyzes fundamental limitations of differential amplifiers in practical environments like VLSI design

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