Electrical Engineering 2023 Paper I 50 marks Solve

Q4

(a) For the circuit shown below, early voltage V_A = ∞ and β = 100. Find the reverse saturation current if: (i) the collector current of Q₁ = 0·5 mA. (ii) Q₁ is biased at the edge of saturation. (20 marks) (b) Consider the control circuitry of a machine copier with four switches as shown below in the figure. These switches are at various points along the path of the machine. Each switch is normally open and closes only when the paper passes over it. Let there be a restriction that switch 1 and switch 4 cannot close simultaneously. Use Karnaugh map to design a logic circuit that produces a high output whenever two or more switches are closed at the same time. (SW1, SW2, SW3, SW4 : Switch 1, Switch 2, Switch 3, Switch 4) (20 marks) (c) The experimental data for the two-port network shown in the figure is given in the table. | | V_S1 Volts | V_S2 Volts | I_1 Amp | I_2 Amp | |---|---|---|---|---| | Experiment 1 | 100 | 50 | 5 | -30 | | Experiment 2 | 50 | 100 | -20 | -5 | | Experiment 3 | 25 | 0 | — | — | | Experiment 4 | — | — | 5 | 0 | Obtain Z-parameters, Y-parameters and fill in the missing data. (10 marks)

हिंदी में प्रश्न पढ़ें

(a) नीचे प्रदर्शित किए गए परिपथ के लिए, अर्ली बोल्टता V_A = ∞ तथा β = 100 है । व्युत्क्रम संतृप्ति धारा ज्ञात कीजिए यदि : (i) Q₁ की संग्राहक धारा 0·5 mA है । (ii) Q₁ संतृप्तता के छोर पर बायस्ड है । (20 marks) (b) नीचे चित्र में दी गई चार सिवचों के साथ प्रतिलिपिक यंत्र की नियंत्रक परिपथिकी पर विचार कीजिए । ये सिवच यंत्र के मार्ग में विभिन्न बिन्दुओं पर स्थित हैं । प्रत्येक सिवच सामान्यतः खुला रहता है और केवल तब बंद होता है, जब उसके ऊपर से कागज़ गुज़रता है । सिवच 1 तथा सिवच 4 का एक साथ बंद होना प्रतिबंधित है । कारना मानचित्र का उपयोग करते हुए एक तर्क परिपथ अभिकल्पित कीजिए जो दो अथवा दो से अधिक सिवचों के एक साथ बंद होने की दशा में उच्च निगत उत्पन्न करे । (SW1, SW2, SW3, SW4 : सिवच 1, सिवच 2, सिवच 3, सिवच 4) (20 marks) (c) चित्र में प्रदर्शित द्वि-प्रदार तंत्र के लिए प्रयोगात्मक आँकड़े तालिका में दिए गए हैं। Z-प्राचल, Y-प्राचल ज्ञात कीजिए तथा तालिका में अनुपलब्ध आँकड़े भरिए। | | V_S1 Volts | V_S2 Volts | I_1 Amp | I_2 Amp | |---|---|---|---|---| | प्रयोग 1 | 100 | 50 | 5 | -30 | | प्रयोग 2 | 50 | 100 | -20 | -5 | | प्रयोग 3 | 25 | 0 | — | — | | प्रयोग 4 | — | — | 5 | 0 | (10 marks)

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Approach

Solve this multi-part numerical and design problem by allocating approximately 40% of effort to part (a) given its 20 marks, 40% to part (b) for its 20 marks, and 20% to part (c) for its 10 marks. Begin with clear circuit diagrams for each part, then apply BJT current equations for (a), use K-map simplification with the given constraint for (b), and apply two-port network parameter conversions for (c). Conclude with verification of results and practical significance.

Key points expected

  • Part (a): Apply Ebers-Moll model with V_A = ∞ (neglect Early effect), use I_C = βI_B/(1+β/β) relationship, and recognize that at edge of saturation V_CE(sat) ≈ 0.2V with I_C/I_B < β
  • Part (a): Calculate reverse saturation current I_S using I_C = I_S exp(V_BE/V_T) for both operating conditions (active mode and edge of saturation)
  • Part (b): Construct 4-variable K-map with SW1, SW2, SW3, SW4 as inputs, identify minterms where two or more switches are closed (at least two 1s in input combination)
  • Part (b): Apply the constraint that SW1 and SW4 cannot close simultaneously (don't care or forbidden condition), simplify using K-map grouping for minimal SOP or POS realization
  • Part (c): Calculate Z-parameters from given experimental data using V1 = z11 I1 + z12 I2 and V2 = z21 I1 + z22 I2, then convert to Y-parameters using matrix inversion
  • Part (c): Determine missing data in Experiments 3 and 4 by substituting known Z-parameters into the network equations

Evaluation rubric

DimensionWeightMax marksExcellentAveragePoor
Concept correctness20%10Correctly identifies active mode vs saturation conditions for (a); properly handles the 'two or more switches' condition and constraint implementation in (b); accurately applies two-port parameter definitions and conversion formulas for (c)Minor errors in BJT region identification or K-map grouping; some confusion between Z and Y parameter definitions but correct final approachFundamental misunderstanding of BJT operation regions, incorrect K-map construction, or inability to distinguish between different two-port parameter sets
Numerical accuracy20%10Precise calculation of I_S values in (a) with correct V_BE at edge of saturation; accurate minterm identification and minimal logic expression in (b); correct Z and Y parameter values with proper unit handling in (c)Minor arithmetic errors or incorrect V_T value usage; one or two incorrect minterms in K-map; small errors in matrix inversion for Y-parametersSignificant calculation errors, wrong order of magnitude for I_S, incorrect parameter extraction from data, or missing units throughout
Diagram quality20%10Clear circuit diagram showing Q1 with labeled terminals for (a); neat 4-variable K-map with properly grouped cells for (b); standard two-port network representation with correct current directions for (c)Diagrams present but with missing labels or unclear terminal markings; K-map drawn but with minor grouping visualization issuesMissing essential diagrams, unrecognizable circuit sketches, or no visual representation of K-map or two-port network
Step-by-step derivation20%10Systematic derivation showing I_C = I_S exp(V_BE/V_T) setup, explicit V_BE calculation for saturation edge, complete K-map filling with constraint notation, and full matrix solution for parameters with determinant calculationSome steps skipped but logical flow maintained; missing intermediate steps in parameter conversion but correct final resultNo visible derivation, jumps to final answers without justification, or completely wrong solution methodology
Practical interpretation20%10Explains significance of I_S in BJT fabrication and temperature dependence; discusses practical implementation of the copier safety logic using standard gates; relates two-port parameters to actual network behavior and measurement techniquesBrief mention of practical relevance without elaboration; standard concluding remarks without specific application contextNo practical context provided, purely mathematical treatment without any connection to real-world BJT applications, digital circuit implementation, or network analysis

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