(a) For the circuit shown below, early voltage V_A = ∞ and β = 100. Find the reverse saturation current if: (i) the collector…

(a) Reverse saturation current of the transistor

Thevenin equivalent of the base bias: V_th = 2.5 × 30/(50 + 30) = 0.9375 V and R_th = 50 ∥ 30 = 18.75 kΩ. The collector resistor is 3 kΩ and the emitter is grounded. Use I_C = I_S e^(V_BE/V_T) with V_T = 26 mV.

(i) I_C = 0.5 mA. I_B = I_C/β = 5 µA, so V_BE = V_th − I_B R_th = 0.9375 − 5 µA × 18.75 kΩ = 0.84375 V. Then V_CE = 2.5 − 0.5 mA × 3 kΩ = 1 V, so the transistor is active and the exponential law applies. I_S = I_C e^(−V_BE/V_T) = 0.5 mA × e^(−0.84375/0.026) = 0.5 mA × e^(−32.45) ≈ 4.0 × 10⁻¹⁸ A.

(ii) Edge of saturation. Here V_CB = 0, so V_C = V_B = V_BE. The collector equation gives I_C = (2.5 − V_BE)/3 kΩ, and the base gives V_BE = 0.9375 − 18.75 kΩ × I_C/100 = 0.9375 − 187.5 I_C. Substituting: 3000 I_C = 2.5 − 0.9375 + 187.5 I_C, so 2812.5 I_C = 1.5625 and I_C = 0.5556 mA. Then V_BE = 0.9375 − 0.1042 = 0.8333 V, and I_S = 0.5556 mA × e^(−0.8333/0.026) ≈ 6.7 × 10⁻¹⁸ A.

The two answers differ because they correspond to different operating points (and hence different devices) for the same bias network.

(b) Logic circuit for "two or more switches closed"

Let A, B, C, D = 1 when SW1 to SW4 are closed. A switch closed connects its line to ground, so the logic circuit sees 0 V for a closed switch and 5 V (through the pull-up resistor) for an open one, and its inputs are the complements of A, B, C, D.

The restriction that SW1 and SW4 cannot close together makes A·D = 1 impossible: minterms 9, 11, 13 and 15 (ABCD = 1001, 1011, 1101, 1111) are don't-cares. The output is 1 for minterms 3, 5, 6, 7, 10, 12, 14 (two or more ones).

Karnaugh map groups (using the don't-cares): AB (12, 14, 13, 15), AC (10, 14, 11, 15), BC (6, 7, 14, 15), BD (5, 7, 13, 15), CD (3, 7, 11, 15). Each is essential because minterms 12, 10, 6, 5 and 3 are covered by one group each.

X = AB + AC + BC + BD + CD, which is every pair of switches except SW1 with SW4.

Implementation. With the inputs V₁ to V₄ as seen by the circuit (complements of A to D), each product term is a NOR of two inputs, for example AB = (V₁ + V₂)'. So X = (V₁ + V₂)' + (V₁ + V₃)' + (V₂ + V₃)' + (V₂ + V₄)' + (V₃ + V₄)': five 2-input NOR gates feeding a 5-input OR gate.

(c) Two-port parameters and missing data

With V₁ = V_S1, V₂ = V_S2, use V = ZI for the two experiments.

(i) Z-parameters. Row 1: 100 = 5z₁₁ − 30z₁₂ and 50 = −20z₁₁ − 5z₁₂, giving z₁₁ = −1.6 Ω and z₁₂ = −3.6 Ω. Row 2: 50 = 5z₂₁ − 30z₂₂ and 100 = −20z₂₁ − 5z₂₂, giving z₂₁ = −4.4 Ω and z₂₂ = −2.4 Ω.

(ii) Y-parameters. Y = Z⁻¹, with det Z = 3.84 − 15.84 = −12 Ω². So y₁₁ = 0.2 S, y₁₂ = −0.3 S, y₂₁ = −0.367 S, y₂₂ = 0.133 S. Check with Experiment 1: I₁ = 0.2 × 100 − 0.3 × 50 = 5 A and I₂ = −0.367 × 100 + 0.133 × 50 = −30 A.

(iii) Missing data. Experiment 3 (V_S1 = 25 V, V_S2 = 0): I₁ = 0.2 × 25 = 5 A and I₂ = −0.367 × 25 = −9.17 A. Experiment 4 (I₁ = 5 A, I₂ = 0): V_S1 = z₁₁ × 5 = −8 V and V_S2 = z₂₁ × 5 = −22 V.

Because z₁₂ ≠ z₂₁, the network is non-reciprocal, so it contains active or dependent elements.