Electrical Engineering 2023 Paper I 50 marks Solve

Paper I — Q3

(a) (i) Consider the shift register shown in the figure below, which is implemented using D flip-flops and 2 : 1…

(a)
(i)

Consider the shift register shown in the figure below, which is implemented using D flip-flops and 2 : 1 multiplexers.

Complete the truth table shown as follows:

InputsNext State
CKCLR̄LoadQ₃Q₂Q₁Q₀
X0X
↑10
↑11

Complete the timing diagram below assuming X₃X₂X₁X₀ = 0101.

(ii)

Use 4 : 1 multiplexer and logic gates to implement the function:

F(A, B, C, D) = Σ m (3, 4, 5, 6, 7, 9, 10, 12, 14, 15) 10 marks

(b)
(i)

The figure shows a triangular pulse which is zero for all time except -a/2 ≤ t ≤ a/2. For this pulse

(I) determine the Fourier transform.

(II) sketch the continuous amplitude spectrum. 10 marks

(ii)

Find L⁻¹[F₁(s) F₂(s)] by using convolution for the following F₁(s) and F₂(s).

F₁(s) = s/(s + 1) F₂(s) = 1/(s² + 1) 10 marks

(c)

An inverting Op-Amp circuit is to be designed such that the weighted sum v₀ = -(v₁ + 4v₂). Resistors R₁, R₂ and R_f are to be chosen in a way that for a maximum output voltage of 4 V, the current in the feedback resistor does not exceed 1 mA.

Calculate the values of R₁, R₂ and R_f. 10 marks

हिंदी में प्रश्न पढ़ें
(a)
(i)

नीचे दिए गए चित्र में प्रदर्शित विस्थापन पंजी जिसे D फ्लिप-फ्लॉपों तथा 2 : 1 बहुसंकेतकों के उपयोग से कार्यान्वित किया गया है, पर विचार कीजिए ।

निम्नानुसार प्रदर्शित सत्य तालिका को पूर्ण कीजिए :

निवेशअगली अवस्था
CKCLR̄भारQ₃Q₂Q₁Q₀
X0X
↑10
↑11

X₃X₂X₁X₀ = 0101 मानते हुए नीचे दिए गए समय (टाइमिंग) आरेख को पूर्ण कीजिए ।

(ii)

4 : 1 बहुसंकेतक तथा तर्क द्वारों की सहायता से निम्न फलन कार्यान्वित कीजिए :

F(A, B, C, D) = Σ m (3, 4, 5, 6, 7, 9, 10, 12, 14, 15) 10 अंक

(b)
(i)

चित्र में एक त्रिभुजाकार स्पंद जो -a/2 ≤ t ≤ a/2 को छोड़कर सभी समयों में शून्य है, दर्शाया गया है। इस स्पंद के लिए

(I) फोरिये रूपांतर ज्ञात कीजिए।

(II) सतत आयाम वर्णक्रम रेखांकित कीजिए। 10 अंक

(ii)

संवलन का उपयोग करते हुए निम्नलिखित F₁(s) तथा F₂(s) के लिए

L⁻¹[F₁(s) F₂(s)] ज्ञात कीजिए।

F₁(s) = s/(s+1) F₂(s) = 1/(s²+1) 10 अंक

(c)

एक प्रतिलोमी संक्रियात्मक प्रवर्धक परिपथ इस तरह से परिकल्पित किया जाना है कि भारित योग v₀ = -(v₁ + 4v₂) हो । R₁, R₂ तथा R_f प्रतिरोधकों का चयन इस प्रकार किया जाना है कि 4 V की अधिकतम निर्गत बोल्टता के लिए पुनर्निवेश प्रतिरोधक में धारा 1 mA से अधिक न हो ।

R₁, R₂ तथा R_f के मान परिकलित कीजिए । 10 अंक

Q3 of the 2023 UPSC Mains Electrical Engineering Paper I, as printed
The question as printed in the 2023 Electrical Engineering paper

The figures printed on the question paper

Cut from the original 2023 Electrical Engineering paper, exactly as the candidates in the hall saw them.

Part (a)
Figure for part (a) of this question
Part (a)
Figure for part (a) of this question
Part (b)
Figure for part (b) of this question
Part (c)
Figure for part (c) of this question

The figure this question refers to, in words

The question paper is a scan and the diagram did not survive as text. This is the figure as read from the original page — every component, value and label — so the question can be worked from the text below.

(a) A timing diagram with a horizontal time axis. There are seven horizontal signal traces labeled on the left. From top to bottom: 'CK', 'CLR' (with a bar over it), 'Load', 'XL', 'Q0', 'Q1', 'Q2', 'Q3'. The 'CK' trace is a square wave with 12 cycles shown. The 'CLR' trace is high for the first 10 cycles of CK, then goes low for the last 2 cycles. The 'Load' trace is low, then goes high for the 2nd and 3rd cycles of CK, then goes low for the remaining cycles. The 'XL' trace is low, then goes high for the 6th and 7th cycles of CK, then goes low for the remaining cycles. The traces for 'Q0', 'Q1', 'Q2', and 'Q3' are blank lines, indicating they need to be completed. Vertical dotted lines align the rising edges of the CK signal with the transitions on the other signals.

(b) A circuit diagram showing four switches labeled SW1, SW2, SW3, and SW4. Each switch is connected in series with a resistor labeled '5 V' (implying a 5V supply or pull-up) to a common input line. The other ends of the switches are connected to ground. The common input line feeds into a rectangular block labeled 'Logic Circuit'. The output of the block is a single line labeled 'X'. Below the diagram, a legend states: (SW1, SW2, SW3, SW4 : Switch 1, Switch 2, Switch 3, Switch 4).

(c) Circuit diagram of a two-port network. A rectangular box labeled 'Network' (or 'तंत्र' in Hindi) is in the center. On the left, a voltage source V_S1 is connected in series with the input port. The positive terminal of V_S1 is at the top. The current I_1 is defined as flowing into the top terminal of the network. On the right, a voltage source V_S2 is connected in series with the output port. The positive terminal of V_S2 is at the top. The current I_2 is defined as flowing into the top terminal of the network from the right side. The bottom terminals of both ports are connected to a common ground line.

Below the circuit is a table with 5 rows and 5 columns. The header row contains: (empty), V_S1 Volts, V_S2 Volts, I_1 Amp, I_2 Amp. Row 1 (Experiment 1): 100, 50, 5, -30 Row 2 (Experiment 2): 50, 100, -20, -5 Row 3 (Experiment 3): 25, 0, -, - Row 4 (Experiment 4): -, -, 5, 0

Model answer

Drafted with AI by UPSC Answer Check against this question's marking rubric, to the expected length. UPSC does not publish answers for Mains — this is one way to score well, not an official key. How we build rubrics and answers.

(a)(i) Shift register: truth table and timing diagram

Each 2:1 multiplexer selects its D input: with Load = 1, D_i = X_i (parallel load); with Load = 0, D₀ = X_L (serial input) and D₁ = Q₀, D₂ = Q₁, D₃ = Q₂ (shift towards Q₃). The flip-flops are cleared asynchronously when CLR̄ = 0.

Truth table (next state Q₃Q₂Q₁Q₀):

(i) CK = X, CLR̄ = 0, Load = X: 0 0 0 0.

(ii) CK = ↑, CLR̄ = 1, Load = 0: Q₃Q₂Q₁Q₀ = Q₂ Q₁ Q₀ X_L, a left shift with X_L entering at Q₀.

(iii) CK = ↑, CLR̄ = 1, Load = 1: Q₃Q₂Q₁Q₀ = X₃ X₂ X₁ X₀, a parallel load.

Timing with X₃X₂X₁X₀ = 0101: at the first rising edge, Load = 1, so Q₃Q₂Q₁Q₀ = 0101 (Q₀ = 1, Q₁ = 0, Q₂ = 1, Q₃ = 0). At the following edges (Load = 0, X_L = 0) the word shifts left: 1010, 0100, 1000, 0000 and stays 0000. When X_L is high at the edges that follow, a 1 enters Q₀ and moves along: 0001, then 0011 at the second such edge. With X_L low again the word continues 0110, 1100, 1000. When CLR̄ falls, all outputs go to 0 at once, without waiting for a clock edge.

Diagram: Completed timing diagram of the 4-bit shift register with parallel load 0101, serial input and asynchronous clear

(a)(ii) Implementing F = Σm(3, 4, 5, 6, 7, 9, 10, 12, 14, 15) with a 4:1 multiplexer

Use A and B as select lines (S₁ = A, S₀ = B) and find each data input as a function of C and D.

(i) AB = 00 (m0 to m3): only m3 is present, so I₀ = C·D.

(ii) AB = 01 (m4 to m7): all four are present, so I₁ = 1.

(iii) AB = 10 (m8 to m11): m9 and m10 are present, so I₂ = C'D + CD' = C ⊕ D.

(iv) AB = 11 (m12 to m15): m12, m14 and m15 are present (m13 is absent), so I₃ = C + D'.

Hardware: one 4:1 multiplexer, an AND gate for I₀, logic 1 for I₁, an XOR gate for I₂, and an inverter with an OR gate for I₃.

Diagram: 4 to 1 multiplexer implementation of F with A and B as select lines and gates for the data inputs

(b)(i) Fourier transform of the triangular pulse

The pulse is f(t) = V₀(1 − 2|t|/a) for |t| ≤ a/2, and zero elsewhere. It is even, so

F(ω) = 2∫₀^(a/2) V₀(1 − 2t/a) cos ωt dt.

Integrating by parts, ∫₀^(a/2) (1 − 2t/a) cos ωt dt = 2(1 − cos(ωa/2))/(aω²), so

F(ω) = (4V₀/(aω²)) (1 − cos(ωa/2)) = (8V₀/(aω²)) sin²(ωa/4) = (V₀a/2) [sin(ωa/4)/(ωa/4)]².

Check: the triangle is the convolution of two rectangles of width a/2, so its transform is the square of a sinc. At ω = 0, F = V₀a/2, the area of the pulse.

(II) Amplitude spectrum. |F(ω)| = (V₀a/2) sinc²(ωa/4). It is a real, non-negative curve, with its maximum V₀a/2 at ω = 0, zeros at ω = ±4πn/a (n = 1, 2, 3…), and side lobes that fall as 1/ω², so it is concentrated within |ω| < 4π/a.

Diagram: Triangular pulse and its continuous amplitude spectrum, a sinc squared with zeros at multiples of 4 pi over a

(b)(ii) Inverse Laplace transform by convolution

F₁(s) = s/(s + 1) = 1 − 1/(s + 1), so f₁(t) = δ(t) − e^(−t); F₂(s) = 1/(s² + 1), so f₂(t) = sin t.

f(t) = f₁ * f₂ = sin t − ∫₀^t e^(−τ) sin(t − τ) dτ.

The integral is ∫₀^t e^(−τ) sin(t − τ) dτ = (1/2)(sin t − cos t + e^(−t)).

Hence f(t) = sin t − (1/2)(sin t − cos t + e^(−t)) = (1/2)(sin t + cos t − e^(−t)) for t ≥ 0.

Check by partial fractions: s/[(s + 1)(s² + 1)] = −(1/2)/(s + 1) + (1/2)(s + 1)/(s² + 1), which gives the same result.

(c) Inverting summer design

For the inverting summer, v₀ = −(R_f/R₁)v₁ − (R_f/R₂)v₂, so R_f/R₁ = 1 and R_f/R₂ = 4.

The feedback current at the maximum output is I_f = |v₀|/R_f = 4 V/R_f ≤ 1 mA, so R_f ≥ 4 kΩ.

Choose R_f = 4 kΩ, which gives R₁ = R_f/1 = 4 kΩ and R₂ = R_f/4 = 1 kΩ. Check: with R_f = 4 kΩ the current at 4 V is exactly 1 mA. Any larger R_f with R₁ = R_f and R₂ = R_f/4 also meets the limit.

How this answer will be evaluated

What earns full marks: All parts fully solved with correct derivations, clear diagrams, and proper units.

Evaluation rubric

Each sub-part is marked on its own, against the marks and word limit printed on the paper.

  1. (a)(i) Complete the truth table and timing diagram of the shift register. 10 marks

    describe— define → structure or process in order → labelled diagram → significance

    Must cover

    • Mux action: Load = 1 parallel load, Load = 0 shift with XL into Q0
    • CLR-bar = 0 gives 0000 asynchronously
    • Shift row: Q3Q2Q1Q0 = Q2 Q1 Q0 XL; load row = X3 X2 X1 X0
    • Timing: 0101 at load edge, then left shifts with XL entering

    Loses marks

    • Treating the register as right-shifting.

    Earns more

    • Marks for the truth table and the waveform states.

    Extra mark

    • Stating asynchronous clear.
  2. (a)(ii) Implement F = Sum m(3,4,5,6,7,9,10,12,14,15) using a 4:1 multiplexer and gates. 10 marks

    calculate— given → formula → substitution → result with units → interpretation

    Must cover

    • A, B as select lines
    • I0 = CD, I1 = 1
    • I2 = C xor D, I3 = C + D'
    • Gate-level connection

    Loses marks

    • Wrong select variables without matching data inputs.

    Earns more

    • Marks for each data input and the circuit.

    Extra mark

    • Showing the minterm grouping table.
  3. (b)(i) Determine the Fourier transform of the triangular pulse and sketch its amplitude spectrum. 10 marks

    derive— given → assumptions → stepwise derivation → result → check

    Must cover

    • f(t) = V0(1 - 2|t|/a) for |t| <= a/2
    • F(w) = (8 V0/(a w^2)) sin^2(w a/4) = (V0 a/2) sinc^2(w a/4)
    • Peak V0 a/2 at w = 0
    • Zeros at w = 4 pi n / a and 1/w^2 decay

    Loses marks

    • Sketching the spectrum without zero locations.

    Earns more

    • Marks for the derivation, result and spectrum features.

    Extra mark

    • Convolution-of-rectangles check.
  4. (b)(ii) Find the inverse Laplace transform of F1(s) F2(s) by convolution. 10 marks

    calculate— given → formula → substitution → result with units → interpretation

    Must cover

    • f1(t) = delta(t) - e^-t
    • f2(t) = sin t
    • Convolution integral evaluated
    • f(t) = (1/2)(sin t + cos t - e^-t)

    Loses marks

    • Dropping the delta term.

    Earns more

    • Marks for the method and correct result.

    Extra mark

    • Partial fraction check.
  5. (c) Design the inverting summer with the given constraint. 10 marks

    calculate— given → formula → substitution → result with units → interpretation

    Must cover

    • Rf/R1 = 1 and Rf/R2 = 4
    • Rf >= 4 kohm from 4 V / 1 mA
    • Rf = 4 kohm, R1 = 4 kohm, R2 = 1 kohm
    • Check of the current limit

    Loses marks

    • Choosing Rf below 4 kohm.

    Earns more

    • Marks for the gain conditions and component values.

    Extra mark

    • Noting larger scaled values also work.
What "Solve" is asking you to do

Choose the method, then carry it through to a final answer. Identifying what kind of problem this is and why that method applies is the first thing marked; a correct figure arrived at invisibly earns almost nothing.

Structure that answers it

Given data and what is required → method chosen, with the reason it applies → set-up (equation, circuit, free body, trial balance) → working, step by step → answer with units and any condition of validity

Where marks are lost

Doing the middle steps mentally and writing only the result. In mathematics papers, a further loss comes from giving a decimal where the exact value in surds or fractions was wanted, or from skipping the justification a part explicitly asks for.

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