Paper I — Q3
(a) (i) Consider the shift register shown in the figure below, which is implemented using D flip-flops and 2 : 1…
Consider the shift register shown in the figure below, which is implemented using D flip-flops and 2 : 1 multiplexers.
Complete the truth table shown as follows:
| Inputs | Next State | |||||
|---|---|---|---|---|---|---|
| CK | CLR̄ | Load | Q₃ | Q₂ | Q₁ | Q₀ |
| X | 0 | X | ||||
| ↑ | 1 | 0 | ||||
| ↑ | 1 | 1 |
Complete the timing diagram below assuming X₃X₂X₁X₀ = 0101.
Use 4 : 1 multiplexer and logic gates to implement the function:
F(A, B, C, D) = Σ m (3, 4, 5, 6, 7, 9, 10, 12, 14, 15) 10 marks
The figure shows a triangular pulse which is zero for all time except -a/2 ≤ t ≤ a/2. For this pulse
(I) determine the Fourier transform.
(II) sketch the continuous amplitude spectrum. 10 marks
Find L⁻¹[F₁(s) F₂(s)] by using convolution for the following F₁(s) and F₂(s).
F₁(s) = s/(s + 1) F₂(s) = 1/(s² + 1) 10 marks
An inverting Op-Amp circuit is to be designed such that the weighted sum v₀ = -(v₁ + 4v₂). Resistors R₁, R₂ and R_f are to be chosen in a way that for a maximum output voltage of 4 V, the current in the feedback resistor does not exceed 1 mA.
Calculate the values of R₁, R₂ and R_f. 10 marks
हिंदी में प्रश्न पढ़ें
नीचे दिए गए चित्र में प्रदर्शित विस्थापन पंजी जिसे D फ्लिप-फ्लॉपों तथा 2 : 1 बहुसंकेतकों के उपयोग से कार्यान्वित किया गया है, पर विचार कीजिए ।
निम्नानुसार प्रदर्शित सत्य तालिका को पूर्ण कीजिए :
| निवेश | अगली अवस्था | |||||
|---|---|---|---|---|---|---|
| CK | CLR̄ | भार | Q₃ | Q₂ | Q₁ | Q₀ |
| X | 0 | X | ||||
| ↑ | 1 | 0 | ||||
| ↑ | 1 | 1 |
X₃X₂X₁X₀ = 0101 मानते हुए नीचे दिए गए समय (टाइमिंग) आरेख को पूर्ण कीजिए ।
4 : 1 बहुसंकेतक तथा तर्क द्वारों की सहायता से निम्न फलन कार्यान्वित कीजिए :
F(A, B, C, D) = Σ m (3, 4, 5, 6, 7, 9, 10, 12, 14, 15) 10 marks
चित्र में एक त्रिभुजाकार स्पंद जो -a/2 ≤ t ≤ a/2 को छोड़कर सभी समयों में शून्य है, दर्शाया गया है। इस स्पंद के लिए
(I) फोरिये रूपांतर ज्ञात कीजिए।
(II) सतत आयाम वर्णक्रम रेखांकित कीजिए। 10 marks
संवलन का उपयोग करते हुए निम्नलिखित F₁(s) तथा F₂(s) के लिए
L⁻¹[F₁(s) F₂(s)] ज्ञात कीजिए।
F₁(s) = s/(s+1) F₂(s) = 1/(s²+1) 10 marks
एक प्रतिलोमी संक्रियात्मक प्रवर्धक परिपथ इस तरह से परिकल्पित किया जाना है कि भारित योग v₀ = -(v₁ + 4v₂) हो । R₁, R₂ तथा R_f प्रतिरोधकों का चयन इस प्रकार किया जाना है कि 4 V की अधिकतम निर्गत बोल्टता के लिए पुनर्निवेश प्रतिरोधक में धारा 1 mA से अधिक न हो ।
R₁, R₂ तथा R_f के मान परिकलित कीजिए । 10 marks
The figures printed on the question paper
Cut from the original 2023 Electrical Engineering paper, exactly as the candidates in the hall saw them.
The figure this question refers to, in words
The question paper is a scan and the diagram did not survive as text. This is the figure as read from the original page — every component, value and label — so the question can be worked from the text below.
(a) A timing diagram with a horizontal time axis. There are seven horizontal signal traces labeled on the left. From top to bottom: 'CK', 'CLR' (with a bar over it), 'Load', 'XL', 'Q0', 'Q1', 'Q2', 'Q3'. The 'CK' trace is a square wave with 12 cycles shown. The 'CLR' trace is high for the first 10 cycles of CK, then goes low for the last 2 cycles. The 'Load' trace is low, then goes high for the 2nd and 3rd cycles of CK, then goes low for the remaining cycles. The 'XL' trace is low, then goes high for the 6th and 7th cycles of CK, then goes low for the remaining cycles. The traces for 'Q0', 'Q1', 'Q2', and 'Q3' are blank lines, indicating they need to be completed. Vertical dotted lines align the rising edges of the CK signal with the transitions on the other signals.
(b) A circuit diagram showing four switches labeled SW1, SW2, SW3, and SW4. Each switch is connected in series with a resistor labeled '5 V' (implying a 5V supply or pull-up) to a common input line. The other ends of the switches are connected to ground. The common input line feeds into a rectangular block labeled 'Logic Circuit'. The output of the block is a single line labeled 'X'. Below the diagram, a legend states: (SW1, SW2, SW3, SW4 : Switch 1, Switch 2, Switch 3, Switch 4).
(c) Circuit diagram of a two-port network. A rectangular box labeled 'Network' (or 'तंत्र' in Hindi) is in the center. On the left, a voltage source V_S1 is connected in series with the input port. The positive terminal of V_S1 is at the top. The current I_1 is defined as flowing into the top terminal of the network. On the right, a voltage source V_S2 is connected in series with the output port. The positive terminal of V_S2 is at the top. The current I_2 is defined as flowing into the top terminal of the network from the right side. The bottom terminals of both ports are connected to a common ground line.
Below the circuit is a table with 5 rows and 5 columns. The header row contains: (empty), V_S1 Volts, V_S2 Volts, I_1 Amp, I_2 Amp. Row 1 (Experiment 1): 100, 50, 5, -30 Row 2 (Experiment 2): 50, 100, -20, -5 Row 3 (Experiment 3): 25, 0, -, - Row 4 (Experiment 4): -, -, 5, 0
Model answer
Written by UPSC Answer Check against this question's marking rubric, to the expected length. UPSC does not publish answers for Mains — this is one way to score well, not an official key.
(a) (i) For the given 4-bit D flip-flop shift register, CLR̄ is active-low asynchronous clear. The 2:1 mux at each D input selects the shift input for Load = 0 and the parallel input for Load = 1. In shift mode the D inputs are D₃=Q₂, D₂=Q₁, D₁=Q₀, D₀=Xₗ; in load mode they are D₃=X₃, D₂=X₂, D₁=X₁, D₀=X₀. If CK is not a rising edge and CLR̄=1, the state is held.
- CK = X, CLR̄ = 0, Load = X: Q₃Q₂Q₁Q₀ = 0000.
- CK = ↑, CLR̄ = 1, Load = 0: Q₃Q₂Q₁Q₀ = Q₂Q₁Q₀Xₗ.
- CK = ↑, CLR̄ = 1, Load = 1: Q₃Q₂Q₁Q₀ = X₃X₂X₁X₀.
Assume the initial state is 0000. With X₃X₂X₁X₀=0101, Load high at CK₂ and CK₃, Xₗ high at CK₆ and CK₇, and CLR̄ low from cycle 11:
- after CK₁: 0000
- after CK₂ and CK₃: 0101
- after CK₄: 1010
- after CK₅: 0100
- after CK₆: 1001
- after CK₇: 0011
- after CK₈: 0110
- after CK₉: 1100
- after CK₁₀: 1000
- when CLR̄ falls: 0000, and it remains 0000 through CK₁₂.
Draw Q₃, Q₂, Q₁, Q₀ as square waves taking these values at the aligned CK rising edges; all fall to 0 immediately when CLR̄ falls.
(a) (ii) Use a 4:1 MUX with select S₁S₀=AB. Expand F in A and B.
- AB=00: minterms 0,1,2,3; only m3 is 1, so I₀=CD.
- AB=01: minterms 4,5,6,7; all are 1, so I₁=1.
- AB=10: minterms 8,9,10,11; m9 and m10 are 1, so I₂=C̄D+CD̄=C⊕D.
- AB=11: minterms 12,13,14,15; m12,m14,m15 are 1, so I₃=C+D̄.
Connect A to S₁, B to S₀. The gates are one AND for I₀, one XOR for I₂, one inverter and one OR for I₃; I₁ is tied to 1. Final: F is the MUX output with I₀=CD, I₁=1, I₂=C⊕D, I₃=C+D̄.
(b) (i) Use X(ω)=∫ x(t)exp(-jωt)dt. Let the triangular pulse have peak height A: x(t)=A(1-2|t|/a) for |t|≤a/2, else 0. It is even, so X(ω)=2A∫ from 0 to a/2 (1-2t/a)cos(ωt)dt. Using ∫cos(ωt)dt=sin(ωt)/ω and ∫t cos(ωt)dt=t sin(ωt)/ω+cos(ωt)/ω², X(ω)=2A[sin(ωa/2)/ω-(2/a)((a/2)sin(ωa/2)/ω+(cos(ωa/2)-1)/ω²)] = (4A/a)(1-cos(ωa/2))/ω² = (8A/a)sin²(ωa/4)/ω². Using 1-cosθ=2sin²(θ/2), (I) X(ω)= (Aa/2)sinc²(ωa/4), where sinc x=sin x/x; X(0)=Aa/2 by limit. For unit height, A=1. (II) The amplitude spectrum is |X(ω)|=(Aa/2)sinc²(ωa/4). Sketch an even, non-negative curve: maximum Aa/2 at ω=0; first zeros at ω=±4π/a; next zeros at ±8π/a, ±12π/a; main lobe between -4π/a and 4π/a; side lobes between successive zeros decrease as 1/ω².
(b) (ii) By the convolution theorem, y(t)=L⁻¹[F₁(s)F₂(s)]=∫ from 0 to t f₁(τ)f₂(t-τ)dτ for causal f₁,f₂. F₁(s)=s/(s+1)=1-1/(s+1), so f₁(t)=δ(t)-exp(-t)u(t). F₂(s)=1/(s²+1), so f₂(t)=sin t u(t). Thus y(t)=∫ from 0 to t [δ(τ)-exp(-τ)]sin(t-τ)dτ = sin t - ∫ from 0 to t exp(-τ)sin(t-τ)dτ. Let u=t-τ: ∫ from 0 to t exp(-τ)sin(t-τ)dτ = exp(-t)∫ from 0 to t exp(u)sin u du = exp(-t)[½exp(u)(sin u-cos u)] from 0 to t = ½(sin t-cos t)+½exp(-t). Therefore y(t)=½(sin t+cos t-exp(-t))u(t). Check: partial fractions give Y(s)=-½/(s+1)+½s/(s²+1)+½/(s²+1), the same inverse.
(c) For an ideal inverting summing amplifier, the inverting input is a virtual ground. KCL at that node gives v₁/R₁+v₂/R₂+v₀/Rf=0, so v₀=-(Rf/R₁)v₁-(Rf/R₂)v₂. To obtain v₀=-(v₁+4v₂), match coefficients: Rf/R₁=1, Rf/R₂=4, hence R₁=Rf and R₂=Rf/4. The current in Rf has magnitude |v₀|/Rf because the inverting node is at 0 V. For |v₀|max=4 V and |i|max=1 mA, Rf≥4 V/1 mA=4 kΩ. Taking the limiting value gives the minimum resistor set. Rf=4 kΩ, R₁=4 kΩ, R₂=1 kΩ. Condition: ideal op-amp, virtual ground, no input bias current, output within ±4 V.
What "Solve" is asking you to do
Choose the method, then carry it through to a final answer. Identifying what kind of problem this is and why that method applies is the first thing marked; a correct figure arrived at invisibly earns almost nothing.
Structure that answers it
Given data and what is required → method chosen, with the reason it applies → set-up (equation, circuit, free body, trial balance) → working, step by step → answer with units and any condition of validity
Where marks are lost
Doing the middle steps mentally and writing only the result. In mathematics papers, a further loss comes from giving a decimal where the exact value in surds or fractions was wanted, or from skipping the justification a part explicitly asks for.
How this answer will be evaluated
Approach
(a(i)) calculate: given > formula > substitution > result with units > interpretation | (a(ii)) calculate: given > formula > substitution > result with units > interpretation | (b(i)) derive: given > assumptions > stepwise derivation > result > check | (b(ii)) calculate: given > formula > substitution > result with units > interpretation | (c) calculate: given > formula > substitution > result with units > interpretation Full marks: All parts fully solved with correct derivations, clear diagrams, and proper units.
Key points expected
- Truth table: CLR=0 forces Q3Q2Q1Q0 to 0000
- Truth table: Load=0 causes right shift (Q0=0)
- Truth table: Load=1 loads X3X2X1X0 into Q3Q2Q1Q0
- Timing diagram: Q0-Q3 transitions match Load/CLR logic
- Select variables (e.g., A,B) for MUX inputs
- Derive logic expressions for D0-D3 from minterms
- Draw MUX circuit with correct input connections
- Include necessary logic gates for non-constant inputs
Evaluation rubric
Each sub-part is marked on its own, against the marks and word limit printed on the paper.
- (a(i)) Complete truth table and timing diagram for the shift register. 10 marks
calculate— given → formula → substitution → result with units → interpretation
Must cover
- Truth table: CLR=0 forces Q3Q2Q1Q0 to 0000
- Truth table: Load=0 causes right shift (Q0=0)
- Truth table: Load=1 loads X3X2X1X0 into Q3Q2Q1Q0
- Timing diagram: Q0-Q3 transitions match Load/CLR logic
Loses marks
- Confusing active-low CLR with active-high
- Incorrect shift direction (left vs right)
Earns more
- Correctly identifies rising edge of CK for state change
- Shows Q0-Q3 as 0101 during Load=1 interval
Extra mark
- Labels specific clock edges in timing diagram
- (a(ii)) Implement F(A,B,C,D) using a 4:1 multiplexer and logic gates. 10 marks
calculate— given → formula → substitution → result with units → interpretation
Must cover
- Select variables (e.g., A,B) for MUX inputs
- Derive logic expressions for D0-D3 from minterms
- Draw MUX circuit with correct input connections
- Include necessary logic gates for non-constant inputs
Loses marks
- Incorrect mapping of minterms to MUX inputs
- Missing logic gates for complex inputs
Earns more
- Uses K-map to simplify MUX input expressions
- Clearly labels MUX select lines and data inputs
Extra mark
- Provides a truth table verification
- (b(i)) Determine Fourier transform and sketch amplitude spectrum of triangular pulse. 10 marks
derive— given → assumptions → stepwise derivation → result → check
Must cover
- Define f(t) piecewise for -a/2 to a/2
- Set up integral for F(ω) = ∫f(t)e^(-jωt)dt
- Derive result involving sinc²(ωa/4) or similar
- Sketch spectrum showing main lobe and side lobes
Loses marks
- Incorrect limits of integration
- Missing square in the sinc function
Earns more
- Uses even symmetry to simplify integration
- Correctly identifies nulls in the spectrum
Extra mark
- Calculates specific null frequencies
- (b(ii)) Find inverse Laplace transform of F1(s)F2(s) using convolution. 10 marks
calculate— given → formula → substitution → result with units → interpretation
Must cover
- Identify f1(t) = e^(-t) and f2(t) = sin(t)
- Set up convolution integral ∫f1(τ)f2(t-τ)dτ
- Evaluate integral using integration by parts
- Simplify final expression for f(t)
Loses marks
- Incorrect identification of inverse transforms
- Sign errors in integration by parts
Earns more
- Correctly applies limits of integration (0 to t)
- Shows intermediate integration steps clearly
Extra mark
- Verifies result using partial fraction expansion
- (c) Calculate R1, R2, and Rf for the inverting Op-Amp circuit. 10 marks
calculate— given → formula → substitution → result with units → interpretation
Must cover
- Write output equation v0 = -(Rf/R1)v1 - (Rf/R2)v2
- Match coefficients to get Rf/R1 = 1 and Rf/R2 = 4
- Use max current constraint: 4V / Rf ≤ 1mA
- Calculate specific values: Rf=4kΩ, R1=4kΩ, R2=1kΩ
Loses marks
- Incorrect gain formula for inverting amplifier
- Ignoring the current constraint
Earns more
- States assumption of ideal Op-Amp (virtual ground)
- Shows current calculation for feedback resistor
Extra mark
- Checks power dissipation in resistors
Practice this exact question
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