Electrical Engineering 2023 Paper I 50 marks Solve

Q3

(a) (i) Consider the shift register shown in the figure below, which is implemented using D flip-flops and 2 : 1 multiplexers. Complete the truth table shown as follows: | Inputs | | | Next State | | CK | CLR̄ | Load | Q₃ | Q₂ | Q₁ | Q₀ | | X | 0 | X | | | | | | ↑ | 1 | 0 | | | | | | ↑ | 1 | 1 | | | | | Complete the timing diagram below assuming X₃X₂X₁X₀ = 0101. (ii) Use 4 : 1 multiplexer and logic gates to implement the function: F(A, B, C, D) = Σ m (3, 4, 5, 6, 7, 9, 10, 12, 14, 15) (10 marks) (b) (i) The figure shows a triangular pulse which is zero for all time except -a/2 ≤ t ≤ a/2. For this pulse (I) determine the Fourier transform. (II) sketch the continuous amplitude spectrum. (10 marks) (ii) Find L⁻¹[F₁(s) F₂(s)] by using convolution for the following F₁(s) and F₂(s). F₁(s) = s/(s + 1) F₂(s) = 1/(s² + 1) (10 marks) (c) An inverting Op-Amp circuit is to be designed such that the weighted sum v₀ = -(v₁ + 4v₂). Resistors R₁, R₂ and R_f are to be chosen in a way that for a maximum output voltage of 4 V, the current in the feedback resistor does not exceed 1 mA. Calculate the values of R₁, R₂ and R_f. (10 marks)

हिंदी में प्रश्न पढ़ें

(a) (i) नीचे दिए गए चित्र में प्रदर्शित विस्थापन पंजी जिसे D फ्लिप-फ्लॉपों तथा 2 : 1 बहुसंकेतकों के उपयोग से कार्यान्वित किया गया है, पर विचार कीजिए । निम्नानुसार प्रदर्शित सत्य तालिका को पूर्ण कीजिए : | निवेश | | | अगली अवस्था | | CK | CLR̄ | भार | Q₃ | Q₂ | Q₁ | Q₀ | | X | 0 | X | | | | | | ↑ | 1 | 0 | | | | | | ↑ | 1 | 1 | | | | | X₃X₂X₁X₀ = 0101 मानते हुए नीचे दिए गए समय (टाइमिंग) आरेख को पूर्ण कीजिए । (ii) 4 : 1 बहुसंकेतक तथा तर्क द्वारों की सहायता से निम्न फलन कार्यान्वित कीजिए : F(A, B, C, D) = Σ m (3, 4, 5, 6, 7, 9, 10, 12, 14, 15) (10 marks) (b) (i) चित्र में एक त्रिभुजाकार स्पंद जो -a/2 ≤ t ≤ a/2 को छोड़कर सभी समयों में शून्य है, दर्शाया गया है। इस स्पंद के लिए (I) फोरिये रूपांतर ज्ञात कीजिए। (II) सतत आयाम वर्णक्रम रेखांकित कीजिए। (10 marks) (ii) संवलन का उपयोग करते हुए निम्नलिखित F₁(s) तथा F₂(s) के लिए L⁻¹[F₁(s) F₂(s)] ज्ञात कीजिए। F₁(s) = s/(s+1) F₂(s) = 1/(s²+1) (10 marks) (c) एक प्रतिलोमी संक्रियात्मक प्रवर्धक परिपथ इस तरह से परिकल्पित किया जाना है कि भारित योग v₀ = -(v₁ + 4v₂) हो । R₁, R₂ तथा R_f प्रतिरोधकों का चयन इस प्रकार किया जाना है कि 4 V की अधिकतम निर्गत बोल्टता के लिए पुनर्निवेश प्रतिरोधक में धारा 1 mA से अधिक न हो । R₁, R₂ तथा R_f के मान परिकलित कीजिए । (10 marks)

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Approach

Solve this multi-part numerical problem by allocating time proportionally: spend ~40% on part (a) covering shift register truth table, timing diagram and MUX implementation; ~40% on part (b) for Fourier transform derivation with spectrum sketch and convolution integral evaluation; and ~20% on part (c) for Op-Amp resistor design. Begin each sub-part with stated assumptions, show complete derivations with intermediate steps, and conclude with boxed final answers.

Key points expected

  • For (a)(i): Complete truth table showing CLR̄=0 resets all outputs to 0; CLR̄=1, Load=0 enables shift right; CLR̄=1, Load=1 enables parallel load from X₃X₂X₁X₀; timing diagram showing Q outputs tracking 0101 with proper clock edge triggering
  • For (a)(ii): Implement 4-variable function using 4:1 MUX with A,B as select lines, deriving C,D-based data inputs using K-map or Boolean algebra for minterms 3,4,5,6,7,9,10,12,14,15
  • For (b)(I): Derive Fourier transform of triangular pulse X(ω) = (a/2)sinc²(ωa/4π) or equivalent form using integration by parts or known transform pairs
  • For (b)(II): Sketch amplitude spectrum showing |X(ω)| as sinc² function with nulls at ω = ±4π/a, ±8π/a, etc., and peak value a/2 at ω=0
  • For (b)(ii): Evaluate convolution integral for L⁻¹[F₁(s)F₂(s)] = cos(t) - e⁻ᵗ + sin(t) - t·cos(t) or simplified form using convolution theorem with proper limits
  • For (c): Design inverting summer with v₀ = -R_f(v₁/R₁ + v₂/R₂), yielding R_f = 4kΩ, R₁ = 4kΩ, R₂ = 1kΩ satisfying I_f ≤ 1mA at v₀ = 4V

Evaluation rubric

DimensionWeightMax marksExcellentAveragePoor
Concept correctness20%10Correctly identifies shift register modes (reset/shift/load), applies Shannon's expansion for MUX implementation, uses correct Fourier transform definition for triangular pulse, applies convolution theorem properly, and applies virtual ground concept for inverting amplifier designIdentifies basic concepts with minor errors in mode selection, MUX variable assignment, transform limits, or Op-Amp configuration; shows partial understanding of convolution vs multiplication in s-domainConfuses synchronous/asynchronous operation, uses wrong select lines for MUX, applies wrong transform formula, attempts direct multiplication instead of convolution, or uses non-inverting configuration
Numerical accuracy20%10All calculations precise: correct truth table values, accurate minterm coverage for MUX, exact Fourier transform expression, correct convolution integral evaluation with proper algebraic simplification, and resistor values satisfying all constraints with verificationMinor arithmetic errors in timing diagram states, MUX data inputs, transform coefficients, convolution constants, or resistor calculations; final answers close but not exactMajor calculation errors: wrong next states, incorrect minterm implementation, missing 1/2π factors in transform, wrong partial fractions in convolution, or resistor values violating current constraint
Diagram quality15%7.5Clear timing diagram with clock edges, propagation delays indicated, proper alignment of Q₃-Q₀ showing 0101 load then shift; accurate sinc² spectrum sketch with labeled axes, null points, and peak; neat MUX implementation diagram with labeled inputsTiming diagram lacks edge alignment or clarity; spectrum sketch roughly correct but missing key features; functional but messy circuit diagramsMissing diagrams, unlabeled axes, incorrect waveform shapes, straight-line instead of sinc² spectrum, or no circuit schematic for MUX implementation
Step-by-step derivation25%12.5Complete derivations shown: characteristic equation for shift register, K-map reduction for MUX data inputs, integration steps for Fourier transform with limits -a/2 to a/2, convolution integral setup with τ substitution, and simultaneous equations for resistor design with constraint verificationShows key steps but skips some integration details, assumes transform results without derivation, or presents final resistor values without showing constraint equationsOnly final answers stated, no derivation of truth table, missing integration steps, jumps from s-domain to time domain without convolution, or no justification for resistor selection
Practical interpretation20%10Interprets shift register as universal register for serial/parallel conversion, discusses MUX implementation efficiency vs direct gates, explains spectral bandwidth implications of pulse duration, validates convolution result via alternative method, and discusses power dissipation and standard resistor value selection for Op-Amp designBrief mention of practical applications without elaboration; standard value selection mentioned but not justified; no discussion of trade-offsPurely mathematical treatment with no physical interpretation; no discussion of practical constraints like loading, bandwidth, or component selection

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