(a) The figure shows a unity feedback system. The steady-state value of the unit step response c(t) is 0·8. Determine the maximum overshoot in the response c(t) : (10 marks)

(b) A circuit breaker is rated as 2500 A, 1500 MVA, 33 kV, 3 sec, 3-phase,

Question

(a) The figure shows a unity feedback system. The steady-state value of the unit step response c(t) is 0·8. Determine the maximum overshoot in the response c(t) : (10 marks)

(b) A circuit breaker is rated as 2500 A, 1500 MVA, 33 kV, 3 sec, 3-phase, oil circuit breaker. Determine its rated normal current, breaking current, making current and short-time rating (current). (10 marks)

(c) An audio signal, whose bandwidth is 15 kHz, is to be digitized using PCM. Uniform quantization with 1024 levels and binary encoding are assumed. Determine the minimum sampling rate. If the actual sampling rate is 20% excess of the minimum rate, determine the minimum permissible bit rate. (10 marks)

(d) Briefly explain the following logical instructions of 8085 microprocessor : (i) ANA M (ii) XRA M (iii) CMC (iv) STC (v) RRC (10 marks)

(e) In a three-phase 400 km long transmission line, the conductors are spaced at the corners of an equilateral triangle of side 5 m. The diameter of each conductor is 3 cm. Calculate the capacitance per phase of the 400 km long conductor. (10 marks)

UPSC Answer Check · Accepted Answer

(a) For a unity negative feedback system, the closed-loop transfer function is

C(s)/R(s) = G(s)/(1 + G(s)) = [K/((s + 1)(s + 2))] / [1 + K/((s + 1)(s + 2))]

= K/(s^2 + 3s + 2 + K).

For a unit step input, R(s) = 1/s. By the final value theorem,

c(∞) = lim s→0 s C(s) = lim s→0 K/(s^2 + 3s + 2 + K) = K/(2 + K).

Given c(∞) = 0·8,

K/(2 + K) = 0·8

K = 0·8(2 + K) = 1·6 + 0·8K

0·2K = 1·6

K = 8.

Hence the closed-loop denominator is

s^2 + 3s + 2 + 8 = s^2 + 3s + 10.

Compare with the standard second-order denominator s^2 + 2ζω_n s + ω_n^2:

ω_n^2 = 10, so ω_n = √10 rad/s.

2ζω_n = 3, so ζ = 3/(2√10).

The system is underdamped because ζ < 1. Maximum overshoot is

M_p = e^(-πζ/√(1 − ζ^2)) × 100%.

Now 1 − ζ^2 = 1 − 9/40 = 31/40. Therefore

ζ/√(1 − ζ^2) = [3/(2√10)] / [√(31/40)] = 3/√31.

So

M_p = e^(-3π/√31) × 100% ≈ 18·40%.

Maximum overshoot ≈ 18·40%.

(b) For a three-phase circuit breaker, the rated normal current is the given continuous current rating.

Rated normal current = 2500 A.

The rated breaking current is obtained from the three-phase power formula

S = √3 V I.

Here S = 1500 MVA, V = 33 kV.

I_b = 1500 × 10^6 / (√3 × 33 × 10^3) A

I_b = 1500/(√3 × 33) kA = 500√3/33 kA ≈ 26·24 kA rms.

The making current is taken as 2·55 times the rated symmetrical breaking current for a 50 Hz system:

I_m = 2·55 I_b = 2·55 × 500√3/33 kA

I_m = 425√3/11 kA ≈ 66·92 kA peak.

The short-time rating current is the rms short-circuit current the breaker can carry for the specified short time, here 3 sec. It is equal to the rated breaking current.

Rated normal current = 2500 A.

Breaking current = 500√3/33 kA ≈ 26·24 kA rms.

Making current = 425√3/11 kA ≈ 66·92 kA peak.

Short-time rating current = 500√3/33 kA ≈ 26·24 kA rms for 3 sec.

(c) The bandwidth of the audio signal is W = 15 kHz.

By the Nyquist sampling theorem, the minimum sampling rate is

f_s,min = 2W = 2 × 15 kHz = 30 kHz.

Number of quantization levels L = 1024.

1024 = 2^10, so the number of bits per sample is

n = log2 1024 = 10 bits/sample.

The actual sampling rate is 20% in excess of the minimum rate:

f_s = 1·2 × 30 kHz = 36 kHz.

Therefore the minimum permissible bit rate for binary PCM is

R_b = n f_s = 10 × 36,000 = 360,000 bits/s.

Minimum sampling rate = 30 kHz.

Minimum permissible bit rate = 360 kbit/s.

(d) In the following, M denotes the memory location whose address is held in the HL register pair.

(i) ANA M

ANA M performs a bitwise logical AND between the accumulator and the contents of memory location M. The result is stored in the accumulator; the memory content remains unchanged.

Operation: A ← A ∧ (M)

Flags affected: S, Z, and P are updated according to the result. CY and AC are reset. It is commonly used for masking bits.

(ii) XRA M

XRA M performs a bitwise logical exclusive-OR between the accumulator and the contents of memory location M. The result is stored in the accumulator; the memory content remains unchanged.

Operation: A ← A ⊕ (M)

Flags affected: S, Z, and P are updated. CY and AC are reset. It is used to complement selected bits or to clear the accumulator by XORing it with itself.

(iii) CMC

CMC complements the carry flag. If CY = 0, it becomes 1; if CY = 1, it becomes 0.

Operation: CY ← complement of CY

No other flags are affected.

(iv) STC

STC sets the carry flag unconditionally.

Operation: CY ← 1

No other flags are affected.

(v) RRC

RRC rotates the accumulator right by one bit. The least significant bit D0 moves to D7 and also to the carry flag. The other bits shift right by one position.

Operation: D7 ← D0, D6 ← D7, ..., D0 ← D1, and CY ← old D0.

Only the CY flag is affected. Other flags are not changed.

(e) For a symmetrically spaced three-phase transmission line, the capacitance per phase to neutral per unit length is

C_0 = 2π ε0 / ln(D/r) F/m,

where D is the equilateral spacing and r is the conductor radius.

Given:

D = 5 m

Diameter of conductor = 3 cm = 0·03 m

r = 0·03/2 = 0·015 m

ε0 = 8·854 × 10^-12 F/m

Now

D/r = 5/0·015 = 1000/3 ≈ 333·333.

ln(D/r) = ln(1000/3) ≈ 5·80914.

Therefore

C_0 = (2π × 8·854 × 10^-12)/5·80914 F/m

C_0 ≈ 9·5767 × 10^-12 F/m.

For a line length of 400 km = 400 × 10^3 m, the total capacitance per phase is

C = C_0 × 400 × 10^3

C ≈ 9·5767 × 10^-12 × 400 × 10^3 F

C ≈ 3·8307 × 10^-6 F.

Capacitance per phase of the 400 km line ≈ 3·83 μF.

This result assumes symmetric equilateral spacing, negligible ground effect, and negligible corona.

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