(a) Consider a systematic linear block code with binary elements whose parity check equations are p₁ = m₁ + m₂ + m₃ p₂ = m₂ + m₃…

(a) Systematic (8, 4) linear block code

Write the code word as c = [m₁ m₂ m₃ m₄ p₁ p₂ p₃ p₄] = mG, with arithmetic modulo 2.

(i) Matrices. The columns of the parity part P follow the parity equations: p₁ uses m₁, m₂, m₃; p₂ uses m₂, m₃, m₄; p₃ uses m₁, m₃, m₄; p₄ uses m₁, m₂, m₄. Hence G = [I₄ | P], with rows 1 0 0 0 | 1 0 1 1, 0 1 0 0 | 1 1 0 1, 0 0 1 0 | 1 1 1 0 and 0 0 0 1 | 0 1 1 1. The parity check matrix is H = [Pᵀ | I₄], with rows 1 1 1 0 | 1 0 0 0, 0 1 1 1 | 0 1 0 0, 1 0 1 1 | 0 0 1 0 and 1 1 0 1 | 0 0 0 1. Then GHᵀ = 0.

(ii) Detection and correction. The 16 code words have a minimum weight of 4, so d_min = 4. The code detects d_min − 1 = 3 errors and corrects ⌊(d_min − 1)/2⌋ = 1 error.

(iii) Decoding 10100100. The syndrome is s = Hrᵀ. Message bits 1010 give computed parities p₁ = 1 + 0 + 1 = 0, p₂ = 0 + 1 + 0 = 1, p₃ = 1 + 1 + 0 = 0 and p₄ = 1 + 0 + 0 = 1, that is 0101, against the received parity 0100. So s = [0 0 0 1]ᵀ, which equals the eighth column of H. The error is in the last bit, and the transmitted code word is 10100101.

(b) Transmission line, generalised constants

Take V_R = 132/√3 = 76.21 kV per phase, and A = D = 1∠5°, B = 88∠75° Ω.

(i) Sending-end voltage and regulation. The load current is I_R = 40 × 10⁶/(√3 × 132 × 10³ × 0.8) = 218.7 A, at 0.8 lagging, so I_R = 218.7∠−36.87° A. Then V_S = AV_R + BI_R = 76.21∠5° kV + (88 × 218.7)∠(75° − 36.87°) V = 76.21∠5° + 19.25∠38.13° kV. In rectangular form, 75.92 + j6.64 + 15.14 + j11.88 = 91.06 + j18.52 kV, so V_S = 92.92∠11.5° kV per phase, which is 160.9 kV line to line. At no load, V_R0 = V_S/A = 92.92 kV per phase. Regulation = (92.92 − 76.21)/76.21 × 100 = 21.9%.

(ii) Load for V_S = V_R = 132 kV and δ = 30°. The receiving-end power is P_R = (V_S V_R/B) cos(β − δ) − (A V_R²/B) cos(β − α), with β = 75° and α = 5°. So P_R = (132²/88)[cos 45° − cos 70°] = 198 × (0.7071 − 0.3420) = 72.3 MW. Similarly Q_R = (132²/88)[sin 45° − sin 70°] = 198 × (0.7071 − 0.9397) = −46.05 MVAr. The negative sign means the load is leading. Then S = 85.7 MVA and pf = 72.29/85.71 = 0.843 leading.

(c) Interrupt-control instructions of 8085

(i) EI (enable interrupts). It sets the interrupt-enable flip-flop, so INTR, RST 5.5, 6.5 and 7.5 are recognised. The enabling takes effect only after the next instruction is executed, which lets a return sequence finish.

(ii) DI (disable interrupts). It resets the flip-flop, which stops all maskable interrupts. TRAP is non-maskable and stays active.

(iii) SIM (set interrupt mask). The accumulator controls the masks. D0, D1 and D2 mask RST 5.5, 6.5 and 7.5 (1 = masked). D3 is the mask-set enable, which must be 1 for D0–D2 to take effect. D4 resets the RST 7.5 flip-flop. D6 and D7 enable and carry serial data out (SOE, SOD).

(iv) RIM (read interrupt mask). It loads the accumulator with the status. D0–D2 give the current masks, D3 the interrupt-enable flag, D4–D6 the pending RST 5.5, 6.5 and 7.5 requests, and D7 the serial input data (SID).