(a) Write the state and output equations for the system shown in the figure. Choose state variables x₁ and x₂ as shown in the…

(a) State model, controllability and observability

From the figure, the error e = u − x₂ drives two paths: the block −5/(s + 4), whose output is x₁, and a unity-gain path to the output summer. The output is y = x₁ + e, and y is fed through 1/(s − 1) to give x₂.

(i) State equations. From −5/(s + 4): ẋ₁ = −4x₁ − 5e = −4x₁ + 5x₂ − 5u. From 1/(s − 1): ẋ₂ = x₂ + y. The output is y = x₁ + (u − x₂) = x₁ − x₂ + u. Substituting, ẋ₂ = x₂ + x₁ − x₂ + u = x₁ + u.

So ẋ = Ax + Bu, y = Cx + Du, with A = [−4 5; 1 0], B = [−5; 1], C = [1 −1], D = 1.

(ii) Controllability. AB = [(−4)(−5) + 5(1); (1)(−5)] = [25; −5]. The matrix [B AB] = [−5 25; 1 −5] has determinant 25 − 25 = 0, rank 1 < 2. The system is not completely controllable.

(iii) Observability. CA = [−4 − 1, 5 − 0] = [−5, 5]. The matrix [C; CA] = [1 −1; −5 5] has determinant 5 − 5 = 0, rank 1 < 2. The system is not completely observable.

(iv) Check. The eigenvalues of A solve s² + 4s − 5 = 0, so s = 1 and s = −5. The transfer function is Y/U = (s − 1)/(s + 5), a first-order function, which shows that the unstable mode at s = 1 cancels in the input-output relation but remains hidden in the state model.

(b)(i) Full decoding and partial decoding

The 8085 has 16 address lines A15–A0. A memory or I/O chip needs a chip-select signal generated from the higher-order lines not used by the chip itself.

(i) Full (absolute) decoding. All the higher-order lines are decoded. Each memory location then has one unique address. Advantages: no address ambiguity or foldback, and the address map stays free for future expansion. Disadvantages: more gates or a larger decoder IC, higher cost and a slightly longer propagation delay.

(ii) Partial decoding. Only some of the higher-order lines are decoded and the rest are don't-care. Advantages: simpler, cheaper hardware and a faster decoder. Disadvantages: the same chip responds to several addresses (foldback or mirror addresses), a part of the address space is wasted, and later expansion needs the circuit to be redesigned.

The two differ in how completely the address is used, so full decoding suits larger systems and partial decoding suits small, fixed systems.

(b)(ii) BCD addition with the DAA instruction

Binary addition of two BCD digits can give a result that is not a valid BCD digit. The instruction DAA (decimal adjust accumulator) corrects the accumulator after ADD, ADC, ADI or ACI. It examines the accumulator and flags: if the low nibble is greater than 9 or AC = 1, it adds 06H; then if the high nibble is greater than 9 or CY = 1, it adds 60H.

Example: add 47 and 38 (BCD).

MVI A, 47H; ADI 38H; DAA; STA 2050H; HLT.

After ADI, A = 47H + 38H = 7FH. The low nibble F is greater than 9, so DAA adds 06H, giving 85H, which is the correct BCD sum 85.

Example with a carry: 78 + 69. After ADI, A = E1H with AC = 1, so DAA adds 06H, giving E7H. The high nibble E is greater than 9, so it adds 60H, giving 47H with CY = 1, which is 147 in BCD. DAA works only after an addition, so BCD subtraction needs a complement method.

(c) Single-core cable

Given: d = 1.6 cm, so r = 0.8 cm; D = 3.2 cm, so D/d = 2, ln 2 = 0.6931; l = 5 km; ρ = 1.5 × 10¹² Ω-m; ε_r = 3.8; V = 6600 V (taken as the rms conductor-to-sheath voltage).

(i) Insulation resistance. R = ρ ln(D/d)/(2πl) = (1.5 × 10¹² × 0.6931)/(2π × 5000) = 3.31 × 10⁷ Ω = 33.1 MΩ.

(ii) Capacitance. C = 2πε₀ε_r l/ln(D/d) = (2π × 8.854 × 10⁻¹² × 3.8 × 5000)/0.6931 = 1.525 × 10⁻⁶ F = 1.525 µF.

(iii) Maximum stress. It occurs at the conductor surface: g_max = V/(r ln(D/d)) = 6600/(0.008 × 0.6931) = 1.19 × 10⁶ V/m = 11.9 kV/cm (rms). The peak value is √2 × 11.9 = 16.8 kV/cm.