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Electrical Engineering 2023 Paper II 50 marks Solve

Paper II — Q6

(a) (i) A power system has two generators with the following cost curves : Generator 1 : C₁(P_g1) = 0.008 P_g1² + 8 P_g1 + 380…

(a)
(i)

A power system has two generators with the following cost curves :

Generator 1 : C₁(P_g1) = 0.008 P_g1² + 8 P_g1 + 380 (thousand rupees/hour)

Generator 2 : C₂(P_g2) = 0.009 P_g2² + 7 P_g2 + 430 (thousand rupees/hour)

The generator limits are

120 MW ≤ P_g1 ≤ 680 MW 60 MW ≤ P_g2 ≤ 550 MW

A load demand of 650 MW is supplied by the generators in an optimal manner. Determine the optimal generation of each generator, neglecting losses in the transmission network. 10 marks

(ii)

A three-bus network is shown in the figure below, indicating the p.u. impedance of each element :

Find the bus admittance matrix, Ybus, of the network. 10 marks

(b)
(i)

Write the steps involved in DMA data transfer. Also describe the functions of 8085 pins which are used in DMA data transfer. 12 marks

(ii)

Write an 8085 assembly language program to read and complement the contents of the flag register. 8 marks

(c)

Find the value of R so that the system shown in the figure is critically damped. V_i(t) is the input voltage and output V_o(t) is the voltage across the capacitance. L = 90 μH, C = 120 nF : 10 marks

हिंदी में प्रश्न पढ़ें
(a)
(i)

एक शक्ति तंत्र में दो जनित्रों (जनरेटर्स) के लागत वक्र निम्नलिखित हैं :

जनित्र 1 : C₁(P_g1) = 0.008 P_g1² + 8 P_g1 + 380 (हजार रुपये प्रति घंटा)

जनित्र 2 : C₂(P_g2) = 0.009 P_g2² + 7 P_g2 + 430 (हजार रुपये प्रति घंटा)

जनित्रों की सीमाएँ हैं

120 MW ≤ P_g1 ≤ 680 MW 60 MW ≤ P_g2 ≤ 550 MW

जनित्रों द्वारा एक 650 MW भार की माँग इष्टतम तरीके से प्रदान की जाती है। संचरण संजाल की हानि (हास) को नगण्य मानते हुए, प्रत्येक जनित्र का इष्टतम उत्पादन ज्ञात कीजिए। 10 अंक

(ii)

एक त्रि-बस संजाल को नीचे चित्र में दर्शाया गया है, जिसमें प्रत्येक अवयव की p.u. प्रतिबाधा दी गई है :

संजाल की बस प्रवेश्यता मैट्रिक्स, Yबस, प्राप्त कीजिए। 10 अंक

(b)
(i)

डी० एम० ए० डाटा स्थानांतरण में निहित क्रमों को लिखिए। 8085 सूक्ष्म-संसाधित्र की उन पिनों के कार्यों का भी वर्णन कीजिए, जो डी० एम० ए० डाटा स्थानांतरण में उपयोग की जाती हैं। 12 अंक

(ii)

8085 का एक संयोजन भाषा प्रोग्राम लिखिए, जो कि फ्लैग पंजी (रजिस्टर) की अंतर्वस्तुओं (कांटेंट्स) को पढ़ता है एवं उनका पूरक होता है। 8 अंक

(c)

प्रतिरोध R का वह मान प्राप्त कीजिए, जिससे कि नीचे चित्र में दर्शाया गया तंत्र क्रांतिकतः अवमंदित हो जाए। Vi(t) निवेश बोल्टता एवं निर्गत Vo(t) संधारित्र के आर-पार बोल्टता है। L = 90 µH, C = 120 nF : 10 अंक

Q6 of the 2023 UPSC Mains Electrical Engineering Paper II, as printed
The question as printed in the 2023 Electrical Engineering paper
Evaluate your answer to this question → See all 2023 Electrical Engineering questions

The figure this question refers to, in words

The question paper is a scan and the diagram did not survive as text. This is the figure as read from the original page — every component, value and label — so the question can be worked from the text below.

(a) A three-bus network with buses labelled 1, 2, and 3 in a horizontal line. Bus 1 connects to bus 2 through a series impedance of j0.25 p.u. Bus 2 connects to bus 3 through a series impedance of -j0.08 p.u. Bus 1 has a shunt impedance of j0.15 p.u. connected to ground. Bus 3 has a shunt impedance of j0.15 p.u. connected to ground. The bus admittance matrix Ybus of the network is to be found.

(c) A series RLC circuit. The input voltage source Vi(t) is connected to a resistor R in series with an inductor L. The output voltage Vo(t) is taken across a capacitor C, which is connected in parallel with the output terminals. The circuit has two input terminals and two output terminals, with the bottom terminals connected together as a common ground. Component values are L = 90 microhenry and C = 120 nanofarad. The value of R is to be determined for critical damping.

Model answer

Written by UPSC Answer Check against this question's marking rubric, to the expected length. UPSC does not publish answers for Mains — this is one way to score well, not an official key.

(a)(i) Use the equal incremental-cost criterion because transmission losses are neglected. At the optimum, dC₁/dPg1 = dC₂/dPg2 = λ, with Pg1 + Pg2 = 650 MW. IC₁ = dC₁/dPg1 = 0.016 Pg1 + 8 IC₂ = dC₂/dPg2 = 0.018 Pg2 + 7 So, 0.016 Pg1 + 8 = 0.018 Pg2 + 7. Substitute Pg2 = 650 − Pg1: 0.016 Pg1 + 8 = 0.018(650 − Pg1) + 7 0.016 Pg1 + 8 = 18.7 − 0.018 Pg1 0.034 Pg1 = 10.7 Pg1 = 10.7/0.034 = 5350/17 = 314.705882 MW. Pg2 = 650 − 5350/17 = 5700/17 = 335.294118 MW. Limits check: 120 ≤ 314.71 ≤ 680 and 60 ≤ 335.29 ≤ 550, so both are valid. λ = 0.016(5350/17) + 8 = 1108/85 = 13.035294 thousand rupees/MWh. Final: Pg1 = 5350/17 MW ≈ 314.71 MW, Pg2 = 5700/17 MW ≈ 335.29 MW.

(a)(ii) For a series element between buses i and j, yij = 1/zij. The diagonal entries include all admittances connected to the bus, while off-diagonal entries are Yij = −yij. y₁₂ = 1/(j0.25) = −j4 p.u. y₂₃ = 1/(−j0.08) = j12.5 = j25/2 p.u. y₁₀ = y₃₀ = 1/(j0.15) = −j20/3 p.u. Thus, Y₁₁ = y₁₀ + y₁₂ = −j20/3 − j4 = −j32/3 Y₂₂ = y₁₂ + y₂₃ = −j4 + j25/2 = j17/2 Y₃₃ = y₂₃ + y₃₀ = j25/2 − j20/3 = j35/6 Y₁₂ = Y₂₁ = −y₁₂ = j4 Y₂₃ = Y₃₂ = −y₂₃ = −j25/2 Y₁₃ = Y₃₁ = 0 Ybus = [ −j32/3 j4 0 ; j4 j17/2 −j25/2 ; 0 −j25/2 j35/6 ] p.u. Equivalently, Ybus = j [ −32/3 4 0 ; 4 17/2 −25/2 ; 0 −25/2 35/6 ] p.u.

(b)(i) Steps in DMA data transfer:

  • The I/O device sends a DMA request to the DMA controller, e.g. 8257.
  • The DMA controller raises the HOLD input of the 8085.
  • The 8085 completes the current machine cycle, releases the address/data/control buses by making them high-impedance, and raises HLDA.
  • The DMA controller becomes bus master. It places the memory address on the address bus and controls MEMR/MEMW and IOR/IOW to transfer data directly between memory and I/O.
  • It increments/decrements the address register and decrements the byte count after each transfer.
  • When the terminal count is reached, the DMA controller sends EOP and removes HOLD. The CPU lowers HLDA and resumes control.

8085 pins used in DMA:

  • HOLD: input; requests the CPU to release the bus.
  • HLDA: output; acknowledges that the CPU has entered the hold state.
  • AD0–AD7 and A8–A15: normally address/data bus; during DMA these are tri-stated and driven by the DMA controller.
  • IO/M, RD, WR: control outputs; tri-stated during HLDA so that the DMA controller can generate its own memory/IO read-write signals.

(b)(ii) The flag register is not directly addressable; it is accessed through PSW. Program: PUSH PSW POP H MOV A,L CMA MOV L,A PUSH H POP PSW HLT Here PUSH PSW saves A and flags. POP H puts the original accumulator in H and the flag byte in L. CMA complements the flag byte, and PUSH H followed by POP PSW writes the complemented flags back into the flag register while restoring A. If only the five defined flags are to be complemented, replace CMA by XRI D5H.

(c) Taking Laplace transform, the series RLC circuit has Z(s) = R + sL + 1/(sC). The output across C is Vo(s) = [1/(sC)] / [R + sL + 1/(sC)] Vi(s) = Vi(s)/(LCs² + RCs + 1). Characteristic equation: LCs² + RCs + 1 = 0 or s² + (R/L)s + 1/(LC) = 0. For critical damping, the discriminant is zero: (R/L)² − 4/(LC) = 0 R = 2√(L/C). Given L = 90 μH = 90×10⁻⁶ H and C = 120 nF = 120×10⁻⁹ F, L/C = (90×10⁻⁶)/(120×10⁻⁹) = 750. R = 2√750 = 2(5√30) = 10√30 Ω. Final: R = 10√30 Ω ≈ 54.77 Ω.

What "Solve" is asking you to do

Choose the method, then carry it through to a final answer. Identifying what kind of problem this is and why that method applies is the first thing marked; a correct figure arrived at invisibly earns almost nothing.

Structure that answers it

Given data and what is required → method chosen, with the reason it applies → set-up (equation, circuit, free body, trial balance) → working, step by step → answer with units and any condition of validity

Where marks are lost

Doing the middle steps mentally and writing only the result. In mathematics papers, a further loss comes from giving a decimal where the exact value in surds or fractions was wanted, or from skipping the justification a part explicitly asks for.

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How this answer will be evaluated

Approach

(a(i)) calculate: given > formula > substitution > result with units > interpretation | (a(ii)) calculate: given > formula > substitution > result with units > interpretation | (b(i)) describe: define > structure or process in order > labelled diagram > significance | (b(ii)) explain: definition/context > points in order > small example > short close | (c) calculate: given > formula > substitution > result with units > interpretation Full marks: All parts show complete method with correct calculations, proper units, and verification steps.

Key points expected

  • Equate incremental costs (dC1/dP1 = dC2/dP2)
  • Apply power balance constraint (P1 + P2 = 650)
  • Solve simultaneous equations for P1 and P2
  • Verify solutions satisfy generator limits
  • Convert given impedances to admittances (y = 1/z)
  • Identify self-admittances (sum of connected branches)
  • Identify mutual admittances (negative of branch admittance)
  • Construct 3x3 Ybus matrix correctly

Evaluation rubric

Each sub-part is marked on its own, against the marks and word limit printed on the paper.

  1. (a(i)) Optimal generation values for two generators meeting 650 MW load. 10 marks

    calculate— given → formula → substitution → result with units → interpretation

    Must cover

    • Equate incremental costs (dC1/dP1 = dC2/dP2)
    • Apply power balance constraint (P1 + P2 = 650)
    • Solve simultaneous equations for P1 and P2
    • Verify solutions satisfy generator limits

    Loses marks

    • Ignoring generator limits in final answer
    • Arithmetic errors in solving linear equations

    Earns more

    • Explicit calculation of incremental cost expressions
    • Check for binding constraints if limits violated

    Extra mark

    • Calculation of total system cost at optimum
  2. (a(ii)) Bus admittance matrix (Ybus) for the 3-bus network. 10 marks

    calculate— given → formula → substitution → result with units → interpretation

    Must cover

    • Convert given impedances to admittances (y = 1/z)
    • Identify self-admittances (sum of connected branches)
    • Identify mutual admittances (negative of branch admittance)
    • Construct 3x3 Ybus matrix correctly

    Loses marks

    • Sign errors in off-diagonal elements
    • Confusing impedance with admittance values

    Earns more

    • Clear labeling of bus numbers in matrix
    • Explicit calculation of individual branch admittances

    Extra mark

    • Verification of matrix symmetry
  3. (b(i)) Steps in DMA transfer and functions of 8085 DMA pins. 12 marks

    describe— define → structure or process in order → labelled diagram → significance

    Must cover

    • Sequence of DMA transfer steps (request to completion)
    • Function of HOLD and HLDA pins
    • Role of DMA controller in bus arbitration
    • Explanation of memory address and data transfer

    Loses marks

    • Omitting HLDA pin function
    • Confusing DMA with interrupt-driven I/O

    Earns more

    • Mention of interrupt generation after transfer
    • Description of bus release mechanism

    Extra mark

    • Diagram of DMA controller interface
  4. (b(ii)) 8085 assembly program to read and complement flag register. 8 marks

    explain— definition/context → points in order → small example → short close

    Must cover

    • Use PUSH PSW to save flags
    • POP into accumulator to read flags
    • Complement accumulator (CMA instruction)
    • Store result or restore flags appropriately

    Loses marks

    • Attempting direct flag register access
    • Missing CMA instruction for complement

    Earns more

    • Proper use of stack for flag manipulation
    • Clear comments explaining each step

    Extra mark

    • Alternative method using RIM/SIM if applicable
  5. (c) Value of R for critical damping in RLC circuit. 10 marks

    calculate— given → formula → substitution → result with units → interpretation

    Must cover

    • Identify circuit as series RLC configuration
    • Apply critical damping condition (α = ω0)
    • Use formula R = 2√(L/C) for series RLC
    • Substitute L=90μH and C=120nF correctly

    Loses marks

    • Using parallel RLC formula instead of series
    • Unit conversion errors in L or C values

    Earns more

    • Derivation of damping factor α and resonant frequency ω0
    • Unit conversion shown explicitly

    Extra mark

    • Verification of damping ratio ζ = 1

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