(a) (i) A power system has two generators with the following cost curves : Generator 1 : C₁(P_g1) = 0.008 P_g1² + 8 P_g1 + 380…

(a)(i) Optimal generation

With losses neglected, the cost is minimised when the incremental costs are equal: dC₁/dP_g1 = dC₂/dP_g2 = λ, with P_g1 + P_g2 = 650 MW.

dC₁/dP_g1 = 0.016P_g1 + 8 and dC₂/dP_g2 = 0.018P_g2 + 7.

Put P_g2 = 650 − P_g1: 0.016P_g1 + 8 = 0.018(650 − P_g1) + 7 = 18.7 − 0.018P_g1, so 0.034P_g1 = 10.7.

P_g1 = 314.7 MW and P_g2 = 335.3 MW. The incremental cost is λ = 0.016 × 314.7 + 8 = 13.04 thousand rupees per MWh. Both values lie within their limits (120–680 MW and 60–550 MW), so no generator is fixed at a limit.

(a)(ii) Bus admittance matrix

From the figure: a shunt j0.15 at bus 1, a line j0.25 between buses 1 and 2, a capacitive element −j0.08 between buses 2 and 3, and a shunt j0.15 at bus 3. The admittances are y₁₀ = 1/j0.15 = −j6.667, y₁₂ = 1/j0.25 = −j4, y₂₃ = 1/(−j0.08) = +j12.5 and y₃₀ = −j6.667 p.u.

Diagonal terms are the sum of the admittances meeting at the bus, and off-diagonal terms are the negative of the connecting admittance:

Y₁₁ = y₁₀ + y₁₂ = −j10.667, Y₂₂ = y₁₂ + y₂₃ = −j4 + j12.5 = j8.5, Y₃₃ = y₂₃ + y₃₀ = j12.5 − j6.667 = j5.833, Y₁₂ = Y₂₁ = −y₁₂ = +j4, Y₂₃ = Y₃₂ = −y₂₃ = −j12.5, and Y₁₃ = Y₃₁ = 0.

So Y_bus = j [−10.667 4 0; 4 8.5 −12.5; 0 −12.5 5.833] p.u.

(b)(i) DMA data transfer

The steps are:

1. The peripheral asks its DMA controller (for example the 8237) for a transfer, and the controller raises the HOLD signal to the 8085.
2. The 8085 finishes the current machine cycle, floats its address, data and control buses, and sends HLDA (hold acknowledge) high.
3. The DMA controller takes over the buses, places the memory address and control signals, and transfers the data between the peripheral and memory, without the CPU.
4. When the block is complete, the controller removes HOLD. The 8085 lowers HLDA, regains the buses and resumes at the next instruction.

The pins involved: HOLD is the input by which the controller requests the bus. HLDA is the output that tells the controller the bus is released. During HLDA the CPU tri-states AD₀–AD₇, A₈–A₁₅, RD, WR, ALE and IO/M, which lets the controller drive them. The READY input is used to match slow memory during the transfer.

(b)(ii) Program to read and complement the flag register

The flags cannot be read directly. PUSH PSW stores A and the flags on the stack, and POP moves the flags into a register.

PUSH PSW; POP H (flags go to L, accumulator to H); MOV A, L; CMA (complement the flag byte); MOV L, A (keep the result); PUSH H; POP PSW (restore the complemented flags, if they are to be written back); HLT.

The flag byte has the form S Z X AC X P X CY. After CMA the register L holds the complemented flags. The unused bits are ignored when loaded back.

(c) Critically damped RLC network

For the series R, L with the output across C, V_o/V_i = 1/(LCs² + RCs + 1). Comparing with s² + 2ζω_n s + ω_n², ω_n = 1/√(LC) and 2ζω_n = R/L.

Critical damping needs ζ = 1, so R = 2√(L/C) = 2√(90 × 10⁻⁶/120 × 10⁻⁹) = 2√750 = 54.8 Ω.