(a) In the circuit given below, find the voltages at point A and point B. 10 marks
(b) Determine the time domain signal x(t) corresponding to the DTFT given below : 10 marks
(c) Draw the output voltage waveform of the circuit given below for 5 V, 50

Question

(a) In the circuit given below, find the voltages at point A and point B. 10 marks
(b) Determine the time domain signal x(t) corresponding to the DTFT given below : 10 marks
(c) Draw the output voltage waveform of the circuit given below for 5 V, 50 Hz ac rms input. Forward voltage drop in diode D₁ is 0·6 V. 10 marks
(d) Design a sequential circuit with two D flip flops A and B and one input X. Let the state of the circuit remain the same for X = 0. However, when X = 1, the circuit goes through the state transitions from 00 to 10 to 11 to 01, back to 00 and then repeats. 10 marks
(e) Calculate Z-parameters for the two-port network given in the circuit diagram. 10 marks

UPSC Answer Check · Accepted Answer

Solve all five sub-parts systematically, allocating approximately 20% time to each part since all carry equal marks. For (a), apply KCL/KVL or nodal analysis; for (b), use inverse DTFT properties; for (c), sketch the rectified waveform showing clipping at 0.6V; for (d), construct state table and derive D flip-flop excitation equations; for (e), use open-circuit impedance measurements. Present each solution with clear circuit diagrams, mathematical steps, and final boxed answers.
- Part (a): Correct application of nodal analysis or superposition theorem to find VA and VB with proper sign conventions
- Part (b): Accurate inverse DTFT calculation using synthesis equation or standard transform pairs, with proper handling of periodicity
- Part (c): Correct peak voltage calculation (5√2 V), identification of conduction angle, and waveform showing 0.6V offset during positive half-cycles
- Part (d): Complete state diagram, state table, excitation table for D flip-flops, and minimized Boolean expressions for DA and DB
- Part (e): Correct application of Z-parameter definitions (z11=V1/I1 at I2=0, etc.) with proper mesh or nodal analysis of the two-port network
- All parts: Proper unit handling (volts, ohms, seconds, Hz) and significant figures appropriate for engineering calculations
- Diagrams: Clear labeling of components, nodes, reference directions, and waveform axes with time/voltage scales
- Sequential design: Verification that the designed circuit returns to state 00 after 01 when X=1, maintaining self-starting property

Dimension	Weight	Max marks	Excellent	Average	Poor
Concept correctness	20%	10	Correctly identifies and applies fundamental concepts: KCL/KVL for (a), DTFT properties for (b), diode clipping for (c), state machine design for (d), and two-port parameter definitions for (e); no conceptual errors in any sub-part	Most concepts correctly identified but minor errors in applying superposition, inverse transform pairs, or Z-parameter definitions; understands diode behavior but may confuse half-wave with full-wave	Major conceptual errors such as using Thevenin instead of nodal analysis when inappropriate, confusing DTFT with DFT, or designing incorrect state transitions that don't form the required cycle
Numerical accuracy	20%	10	All numerical values accurate: correct node voltages in (a), precise time-domain expression in (b), exact clipping levels and timing in (c), verified state equations in (d), and correct Z-parameter matrix values in (e)	Minor arithmetic errors in 1-2 sub-parts (e.g., calculation mistakes in complex number operations or matrix inversion) but correct methodology; peak voltage calculation errors in (c)	Significant numerical errors across multiple parts, wrong order of magnitude answers, or failure to convert rms to peak in (c); algebraic mistakes leading to incorrect final answers
Diagram quality	20%	10	Clear, labeled circuit diagrams for (a), (c), (e); accurate state diagram and circuit schematic for (d); properly scaled waveform in (c) showing 50 Hz period, 7.07V peak, and 0.6V clipping with correct conduction angles	Diagrams present but missing some labels or component values; waveform sketch roughly correct but without proper time scaling or voltage levels marked; state diagram drawn but transitions unclear	Missing essential diagrams, unrecognizable sketches, or failure to draw the output waveform in (c); no circuit diagram for the sequential design in (d)
Step-by-step derivation	20%	10	Complete, logical derivation sequence for each part: setup of equations, systematic solution, and clear final answer; for (d) shows state table → excitation table → K-map simplification → logic circuit; all steps examinable and reproducible	Most steps shown but some skipped (e.g., jumping from state table to final equations without excitation table); correct approach but condensed presentation that makes error-checking difficult	Final answers stated without derivation, or illogical sequence of steps; no justification for state assignments or missing inverse DTFT integral setup; appears to guess answers
Practical interpretation	20%	10	Interprets results practically: discusses loading effects in (a), signal reconstruction implications in (b), practical diode selection for 50 Hz operation in (c), self-starting and unused state handling in (d), and reciprocity/symmetry checks in (e); relates to Indian power systems (230V, 50 Hz) where relevant	Brief mention of practical significance in 1-2 parts but superficial; acknowledges diode forward drop impact without discussing power dissipation or component ratings	No physical interpretation of results; treats all problems as purely mathematical exercises without connecting to real circuit behavior, measurement techniques, or engineering applications

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