(a) In the circuit given below, find the voltages at point A and point B. 10 marks (b) Determine the time domain signal x(t)…

(a) Node voltages at A and B

Result: V_A = 1.6 V and V_B = −5.6 V (with respect to G).

Circuit (G = 0 V). The inner triangle's corners are wired to A and B, so the branches are:

• A–P 12 Ω; P–B 6 Ω with the 3 A source in parallel, driving 3 A into P and out of B.
• A–B 9 Ω; A–G 3 Ω; B–G 4 Ω.
• A–G: 6 V (+ at A) in series with 6 Ω, so the current leaving A is (V_A − 6)/6.
• B–G: 4 Ω in series with 12 V (+ at G). The junction sits at −12 V, so the current leaving B is (V_B + 12)/4.

Nodal equations (currents leaving each node = 0).

Node P: (V_P − V_A)/12 + (V_P − V_B)/6 − 3 = 0 → −V_A − 2V_B + 3V_P = 36

Node A: (V_A − V_P)/12 + (V_A − V_B)/9 + V_A/3 + (V_A − 6)/6 = 0 → 25V_A − 4V_B − 3V_P = 36

Node B: (V_B − V_P)/6 + 3 + (V_B − V_A)/9 + V_B/4 + (V_B + 12)/4 = 0 → −4V_A + 28V_B − 6V_P = −216

Solution. Eliminating V_P (equivalently, source-transforming 3 A ∥ 6 Ω into 18 V in series with 6 Ω) gives:

(2/3)V_A − (1/6)V_B = 2 and −(1/6)V_A + (2/3)V_B = −4

Solving these gives V_A = 1.6 V, V_B = −5.6 V and V_P = 8.8 V.

Check (KCL at A). The currents leaving A are −0.6 A (12 Ω), +0.8 A (9 Ω), +0.533 A (3 Ω) and −0.733 A (6 V branch). They sum to 0, so the solution is consistent.

(b) Signal corresponding to the given DTFT

A spectrum in e^(jΩ) is 2π-periodic, so the signal asked for as "x(t)" is the discrete sequence x[n].

Reading the plots over one period (−π < Ω ≤ π):

• The magnitude is |X| = |sin Ω| for |Ω| < π/2. It is 1 at Ω = ±π/2, falls to 0 at Ω = 0, and is zero for π/2 < |Ω| < π.
• The phase is a straight line through the origin that reaches 2π at Ω = π. So arg X = 2Ω, repeating every 2π.

This gives X(e^(jΩ)) = |sin Ω| e^(j2Ω) for |Ω| < π/2, and 0 for π/2 < |Ω| ≤ π.

Inverse DTFT.

x[n] = (1/2π) ∫ from −π/2 to π/2 of |sin Ω| e^(jΩ(n+2)) dΩ

Put m = n + 2. Because |sin Ω| is even, the sine part cancels:

x[n] = (1/π) ∫ from 0 to π/2 of sin Ω cos(mΩ) dΩ = (1/2π)[(1 + sin(mπ/2))/(1 + m) + (1 − sin(mπ/2))/(1 − m)]

This simplifies to

x[n] = [1 − (n+2) sin((n+2)π/2)] / [π(1 − (n+2)²)] for n + 2 ≠ ±1, and x[−1] = x[−3] = 1/(2π).

The linear phase e^(j2Ω) is a two-sample time advance.

Sample values: x[−2] = 1/π ≈ 0.318; x[−1] = x[−3] = 1/(2π) ≈ 0.159; x[0] = x[−4] = −1/(3π) ≈ −0.106; x[1] = x[−5] = −1/(2π) ≈ −0.159; x[2] = x[−6] = −1/(15π) ≈ −0.021. x[n] is real and symmetric about n = −2.

(c) Output waveform (biased clamper)

Identification. C₁ is in series with the signal path and the diode–battery branch is a shunt, so the circuit is a biased positive clamper. D₁ has its anode on the + terminal of the 3 V cell and its cathode on the output line. It conducts only when the output tries to fall below

V_clamp = 3 − 0.6 = 2.4 V

Values.

• Peak input: Vₘ = 5√2 = 7.07 V.
• Period: T = 1/50 = 20 ms.
• Time constant: R₁C₁ = 10 kΩ × 100 µF = 1 s. This is 50T, so C₁ barely discharges within a cycle.

Operation.

• At the negative input peak (−7.07 V), D₁ conducts and holds the output at 2.4 V. C₁ charges to V_C = 2.4 + 7.07 = 9.47 V, with the output side positive, as marked on C₁.
• For the rest of the cycle D₁ is reverse-biased, so v_o = v_in + 9.47 V.
• The output therefore swings from +2.4 V (negative peak, clamped) to 7.07 + 9.47 = 16.54 V, about a DC level of 9.47 V.

The droop through R₁ is only about 0.19 V per cycle and is restored at each negative peak.

(d) Synchronous sequential circuit with two D flip-flops

State diagram. X = 0 holds every state; X = 1 steps 00 → 10 → 11 → 01 → 00. For D flip-flops, D equals the next state.

• 0: A — 0; B — 0; A⁺ = D_A — 0; B⁺ = D_B — 0
• 0: A — 0; B — 1; A⁺ = D_A — 0; B⁺ = D_B — 1
• 0: A — 1; B — 0; A⁺ = D_A — 1; B⁺ = D_B — 0
• 0: A — 1; B — 1; A⁺ = D_A — 1; B⁺ = D_B — 1
• 1: A — 0; B — 0; A⁺ = D_A — 1; B⁺ = D_B — 0
• 1: A — 0; B — 1; A⁺ = D_A — 0; B⁺ = D_B — 0
• 1: A — 1; B — 0; A⁺ = D_A — 1; B⁺ = D_B — 1
• 1: A — 1; B — 1; A⁺ = D_A — 0; B⁺ = D_B — 1

K-map simplification.

• D_A has minterms (X A B) = 2, 3, 4, 6. They group as X′A (m2, m3) and XB′ (m4, m6), so D_A = X′A + XB′.
• D_B has minterms 1, 3, 6, 7. They group as X′B (m1, m3) and XA (m6, m7), so D_B = X′B + XA.

Circuit. Each D input is a 2-to-1 multiplexer selected by X: one inverter, four AND gates and two OR gates, with A, B (and B′) fed back and a common clock.

Verification with X = 1.

• AB = 00 gives D_A = B′ = 1 and D_B = A = 0, so the next state is 10.
• AB = 10 gives 11, AB = 11 gives 01, and AB = 01 gives 00. The required cycle is obtained.

With X = 0, D_A = A and D_B = B, so the state is held.

(e) Z-parameters of the bridged-T network

Network. Call the port-1 top terminal node 1, the port-2 top terminal node 2, and the junction of the two lower 3 Ω resistors node M. The resistors are 3 Ω from 1 to 2 (bridge), 3 Ω from 1 to M, 3 Ω from M to 2, and 3 Ω from M to the common line. With V₁ = Z₁₁I₁ + Z₁₂I₂ and V₂ = Z₂₁I₁ + Z₂₂I₂:

Port 2 open (I₂ = 0).

• Current I₁ reaches M by two paths: directly through 3 Ω, or through 3 Ω + 3 Ω = 6 Ω via node 2.
• Resistance from 1 to M = 3 ∥ 6 = 2 Ω. So Z₁₁ = V₁/I₁ = 2 + 3 = 5 Ω.
• By current division, the 6 Ω path carries I₁ × 3/9 = I₁/3. With V_M = 3I₁, V₂ = V_M + 3(I₁/3) = 4I₁, so Z₂₁ = 4 Ω.

Port 1 open (I₁ = 0). The network is symmetric about its vertical centre line, so Z₂₂ = Z₁₁ = 5 Ω and Z₁₂ = Z₂₁ = 4 Ω.

[Z] = [ 5 4 ; 4 5 ] Ω

Nodal analysis gives the same values. Z₁₂ = Z₂₁ confirms reciprocity, as expected for a passive resistive network.