(a) Consider the Boolean function: F(A, B, C, D) = Σ m (1, 3, 4, 11, 12, 13, 14, 15). Implement it with a 4-to-1 multiplexer and external gates. Connect inputs A and B to the selection lines. Input to the four data lines is a function of the variable

Question

(a) Consider the Boolean function: F(A, B, C, D) = Σ m (1, 3, 4, 11, 12, 13, 14, 15). Implement it with a 4-to-1 multiplexer and external gates. Connect inputs A and B to the selection lines. Input to the four data lines is a function of the variables C and D which are obtained by expressing F as a function of C and D for each of the four cases when AB = 00, 01, 10 and 11. Functions are to be implemented with external gates. (20 marks)

(b) In the circuit given below, transistors T₁ and T₂ are having V_BE = 0.6 V and β = 499.
(i) Calculate small signal ac voltage gain of the amplifier at 20 Hz and 2 kHz.
(ii) Find dc voltages on collectors of transistors T₁ and T₂ respectively. (20 marks)

(c) Impulse response of an LTI system, h(n) is defined in the interval N₀ ≤ n ≤ N₁. If the input x(n) to the LTI system is zero except in the interval N₂ ≤ n ≤ N₃, find the interval for which the output y(n) exists in forms of N₀, N₁, N₂ and N₃. (10 marks)

UPSC Answer Check · Accepted Answer

Solve this multi-part problem by allocating time proportionally to marks: approximately 40% on part (a) multiplexer design, 40% on part (b) transistor amplifier analysis, and 20% on part (c) LTI system interval calculation. Begin with clear K-map derivation for (a), proceed to complete DC and AC analysis for (b) including frequency-dependent gain calculations, and conclude with rigorous mathematical derivation of convolution intervals for (c).
- For (a): Construct 4-variable K-map for F(A,B,C,D) = Σm(1,3,4,11,12,13,14,15), group minterms, and express F as function of C,D for each AB combination (00,01,10,11) to determine multiplexer data inputs
- For (a): Draw 4-to-1 MUX with A,B as select lines and implement derived C,D functions using external AND/OR/NOT gates for each data input
- For (b)(i): Calculate DC operating point (ICQ, VCEQ), then determine small-signal parameters (gm, rπ), and compute voltage gain at 20 Hz (considering coupling/bypass capacitor effects) and 2 kHz (mid-band)
- For (b)(ii): Determine VC1 and VC2 using KVL analysis with given VBE = 0.6V and β = 499, accounting for transistor biasing network
- For (c): Apply convolution sum property y(n) = x(n)*h(n) to derive output interval [N₀+N₂, N₁+N₃] with proper justification using support interval mathematics

Dimension	Weight	Max marks	Excellent	Average	Poor
Concept correctness	20%	10	Correctly applies Shannon's expansion theorem for MUX implementation in (a); accurately identifies hybrid-π model and frequency response regions for (b); precisely states convolution interval theorem for (c) with proper closed/open interval handling	Basic K-map reduction correct but MUX implementation partially flawed; transistor amplifier concepts understood but misses frequency-dependent effects; LTI interval concept known but derivation contains boundary errors	Fundamental misunderstanding of multiplexer as function generator; confuses DC and AC analysis or ignores β in calculations; fails to recognize convolution as basis for interval determination
Numerical accuracy	20%	10	All calculations precise: correct minterm-to-function conversions in (a); accurate gain values at both frequencies (typically \|Av\| ≈ 20-50 range) and VC1, VC2 within ±0.1V in (b); exact interval bounds [N₀+N₂, N₁+N₃] in (c)	Minor arithmetic errors in K-map grouping or gate implementation; gain calculations correct at one frequency only or VC values within ±0.5V; interval endpoints correct but notation sloppy	Significant calculation errors leading to wrong data inputs for MUX; order-of-magnitude errors in gain or impossible VC values (negative or exceeding VCC); completely wrong interval formula
Diagram quality	20%	10	Clear, labeled 4-to-1 MUX schematic with A,B→S1,S0, explicit C/D gate networks for D0-D3 in (a); complete two-stage amplifier circuit with proper hybrid-π small-signal equivalent in (b); illustrative timing/sequence diagram for LTI convolution in (c)	MUX diagram present but gate connections unclear; amplifier circuit drawn but missing some labels or small-signal model incomplete; minimal or generic diagram for (c)	Missing or unrecognizable MUX implementation; no circuit diagram for amplifier; no visual representation for any part of the question
Step-by-step derivation	20%	10	Explicit stepwise: K-map → minterm grouping → F(C,D) for each AB case → gate realization in (a); DC analysis → Q-point → small-signal parameters → gain formula → frequency substitution in (b); formal proof of y(n) interval using support properties in (c)	Some intermediate steps skipped in K-map or MUX derivation; DC analysis shown but AC derivation jumps to final formula; interval result stated with minimal justification	Only final answers with no derivation; or incorrect derivation with no logical flow between steps; no mathematical justification for interval result
Practical interpretation	20%	10	Discusses why MUX-based implementation reduces IC count versus full SOP realization; explains significance of gain variation with frequency (lower gain at 20 Hz due to capacitive coupling) and practical biasing considerations; relates LTI interval property to real-time DSP system causality and buffer sizing in Indian ISRO/DRDO applications	Brief mention of hardware advantages for MUX; notes frequency affects gain without explaining mechanism; minimal physical interpretation of interval result	No practical context provided; purely mathematical treatment without engineering significance; or irrelevant discussion unrelated to the circuits and systems analyzed

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