(a) Consider the Boolean function: F(A, B, C, D) = Σ m (1, 3, 4, 11, 12, 13, 14, 15). Implement it with a 4-to-1 multiplexer and…

(a)

• Method: Shannon expansion for a 4-to-1 multiplexer. Take A as the most significant select line and B as the least significant select line. Then F = A′B′I₀ + A′B I₁ + AB′I₂ + AB I₃.
• For AB = 00, the relevant minterms are m₀, m₁, m₂, m₃. From the given list, m₁ and m₃ are 1, while m₀ and m₂ are 0. In C,D order 00, 01, 10, 11 this is 0, 1, 0, 1, so I₀ = C′D + CD = D.
• For AB = 01, the relevant minterms are m₄, m₅, m₆, m₇. Only m₄ is 1. In C,D order this is 1, 0, 0, 0, so I₁ = C′D′.
• For AB = 10, the relevant minterms are m₈, m₉, m₁₀, m₁₁. Only m₁₁ is 1. In C,D order this is 0, 0, 0, 1, so I₂ = CD.
• For AB = 11, the relevant minterms are m₁₂, m₁₃, m₁₄, m₁₅. All four are 1, so I₃ = 1.
• Verification: A′B′D gives m₁ + m₃; A′BC′D′ gives m₄; AB′CD gives m₁₁; AB gives m₁₂ + m₁₃ + m₁₄ + m₁₅. This reproduces the original sum of minterms.
• External gates: D goes directly to I₀; C′ and D′ are formed by inverters and ANDed for I₁; C and D are ANDed for I₂; I₃ is tied to logic 1. The MUX select lines are A and B. Final MUX data inputs: I₀ = D, I₁ = C′D′, I₂ = CD, I₃ = 1.

(b)

Circuit reading. The printed two-stage amplifier is the classic RC-coupled common-emitter pair. T₁'s collector load is R₁ = 9.1 kΩ; T₁'s emitter returns to ground through R₅ = 200 Ω + R₆ = 1.3 kΩ with C₄ = 3.3 µF bypassing R₆; R₃ = 36 kΩ (with C₂ = 10 µF in parallel) couples T₁'s collector to T₂'s base and furnishes the dc bias path for T₂; R₄ = 100 kΩ feeds T₂'s emitter voltage back to T₁'s base. T₂'s collector load is R₂ = 2 kΩ, its emitter resistor R₇ = 1 kΩ is bypassed by C₅ = 100 µF, and the output is taken through C₃ = 100 µF across R_L = 10 kΩ. V_CC = 12 V, V_BE = 0.6 V, β = 499 (α ≈ 0.998, so I_C ≈ I_E).

(ii) DC analysis. T₂ base loop: V_B2 = V_C1 − I_B2R₃, V_E2 = V_B2 − 0.6, I_E2 = V_E2/R₇, I_B2 = I_E2/500. T₁: V_B1 = V_E2 − I_B1R₄, V_E1 = V_B1 − 0.6, I_E1 = V_E1/(R₅+R₆), I_B1 = I_E1/500, and V_C1 = V_CC − (αI_E1 + I_B2)R₁, since R₁ carries T₁'s collector current and T₂'s base current. Solving simultaneously: I_E1 ≈ 0.98 mA and I_E2 ≈ 2.27 mA, giving V_E1 ≈ 1.47 V, V_B1 ≈ 2.07 V, V_E2 ≈ 2.27 V, V_B2 ≈ 2.87 V, and the required collector voltages V_C1 = V_B2 + I_B2R₃ ≈ 2.87 + 0.16 ≈ 3.0 V and V_C2 = 12 − αI_E2R₂ ≈ 7.5 V.

(i) Small-signal gains (source assumed ideal, so R₄ does not load the input). r_e′ = 26 mV/I_E gives r_e1 ≈ 26.3 Ω and r_e2 ≈ 11.4 Ω.

• 2 kHz (mid-band). X_C4 ≈ 24 Ω, X_C5 ≈ 0.8 Ω and X_C2 ≈ 8 Ω are negligible, so R₆ and R₇ are bypassed and R₃ is shorted by C₂ (R₃ is in series in the signal path, not a shunt). Stage 2 input resistance = r_π2 = 500 × 11.4 ≈ 5.7 kΩ, so T₁'s load is R₁ ∥ r_π2 ≈ 3.5 kΩ. A_v1 = −3.5 k/(R₅ + r_e1) = −3.5 k/226 ≈ −15.4; A_v2 = −(R₂ ∥ R_L)/r_e2 = −1.67 k/11.4 ≈ −146. With two inversions, A_v(2 kHz) ≈ +2.2 × 10³ (≈ 67 dB).
• 20 Hz. The bypass capacitors no longer short their resistors. Their corner frequencies are set by the small resistance looking into the emitters, not by R₆ or R₇: for C₅, 1/[2π × 100 µF × (R₇ ∥ r_e2)] ≈ 140 Hz, and for C₄, 1/[2π × 3.3 µF × (R₆ ∥ (R₅ + r_e1))] ≈ 250 Hz, so at 20 Hz both stages have substantial emitter degeneration. Stage 2: Z_E2 = R₇ ∥ X_C5 (X_C5 ≈ 80 Ω) ≈ 6 − j79 Ω, so |A_v2| = 1.67 k/|r_e2 + Z_E2| ≈ 1.67 k/81 ≈ 21, and T₂'s input impedance rises to about 500 × 81 ≈ 40 kΩ, so T₁'s load returns almost to R₁. Stage 1: Z_E1 = 200 + (1.3 k ∥ X_C4, X_C4 ≈ 2.4 kΩ) ≈ 1.2 kΩ in magnitude, giving |A_v1| ≈ 6.3. The coupling capacitors (corners about 1–2 Hz) have little effect. Hence |A_v(20 Hz)| ≈ 6.3 × 21 ≈ 1.3 × 10² (≈ 42 dB), about 25 dB below the mid-band gain, the fall coming from the partial loss of emitter bypass in both stages.

(c)

• Method: support of discrete convolution. The output is y(n) = Σ x(k) h(n-k).
• A term can be nonzero only when x(k) is nonzero and h(n-k) is nonzero. The given supports are N₂ ≤ k ≤ N₃ and N₀ ≤ n-k ≤ N₁.
• The second condition is equivalent to n-N₁ ≤ k ≤ n-N₀. Hence a nonzero term requires the intersection [N₂, N₃] ∩ [n-N₁, n-N₀] to be non-empty.
• Non-emptiness requires both N₂ ≤ n-N₀ and n-N₁ ≤ N₃. These give n ≥ N₀ + N₂ and n ≤ N₁ + N₃.
• Conversely, for any integer n satisfying N₀+N₂ ≤ n ≤ N₁+N₃, choose k = max(N₂, n-N₁). This k also satisfies k ≤ N₃ and k ≤ n-N₀, so at least one convolution term lies inside both supports. Thus the output can exist throughout the whole interval.
• Therefore, assuming N₀ ≤ N₁ and N₂ ≤ N₃, the output interval is N₀ + N₂ ≤ n ≤ N₁ + N₃.
• If either input or impulse-response interval is empty, the output is empty; if endpoint values are zero, the actual nonzero support may be a subinterval, but the possible output interval is the one above.