Paper I — Q3
(a) Consider the Boolean function: F(A, B, C, D) = Σ m (1, 3, 4, 11, 12, 13, 14, 15). Implement it with a 4-to-1 multiplexer and…
Consider the Boolean function: F(A, B, C, D) = Σ m (1, 3, 4, 11, 12, 13, 14, 15). Implement it with a 4-to-1 multiplexer and external gates. Connect inputs A and B to the selection lines. Input to the four data lines is a function of the variables C and D which are obtained by expressing F as a function of C and D for each of the four cases when AB = 00, 01, 10 and 11. Functions are to be implemented with external gates. 20 marks
In the circuit given below, transistors T₁ and T₂ are having V_BE = 0.6 V and β = 499. Calculate small signal ac voltage gain of the amplifier at 20 Hz and 2 kHz.
Find dc voltages on collectors of transistors T₁ and T₂ respectively. 20 marks
Impulse response of an LTI system, h(n) is defined in the interval N₀ ≤ n ≤ N₁. If the input x(n) to the LTI system is zero except in the interval N₂ ≤ n ≤ N₃, find the interval for which the output y(n) exists in forms of N₀, N₁, N₂ and N₃. 10 marks
हिंदी में प्रश्न पढ़ें
बूलिय फलन F(A, B, C, D) = Σ m (1, 3, 4, 11, 12, 13, 14, 15) पर विचार कीजिए। इसका 4 से 1 बहुसंकेतक तथा बाह्य कपाटों (गेट्स) से कार्यान्वयन कीजिए। निवेश A तथा B को चयन पंक्तियों से संयोजित कीजिए। चारों आंकड़ा लाइनों में निवेश, चर C और D का फलन है जिसे प्रत्येक चारों परिस्थितियों AB = 00, 01, 10 तथा 11 में F को C और D के फलन के रूप में व्यक्त कर प्राप्त किया जाता है। फलन का कार्यान्वयन बाह्य कपाटों (गेटों) द्वारा करना है। (20 अंक)
नीचे दिए गए परिपथ में, ट्रांजिस्टर T₁ तथा T₂ के लिए V_BE = 0.6 V और β = 499 है। प्रवर्धक की 20 Hz और 2 kHz पर लघु संकेत ac वोल्टता लाभ संगणित कीजिए।
क्रमशः ट्रांजिस्टर T₁ तथा T₂ के कलेक्टरों पर dc वोल्टता ज्ञात कीजिए। (20 अंक)
एक LTI तंत्र की आवेग अनुक्रिया h(n), अंतराल N₀ ≤ n ≤ N₁ में परिभाषित है। यदि अंतराल N₂ ≤ n ≤ N₃ को छोड़कर LTI तंत्र में निवेश x(n) शून्य है, तो वह अंतराल ज्ञात कीजिए जिसके लिए निर्गत y(n) का अस्तित्व N₀, N₁, N₂ और N₃ के फलन के रूप में है। (10 अंक)
The figure this question refers to, in words
The question paper is a scan and the diagram did not survive as text. This is the figure as read from the original page — every component, value and label — so the question can be worked from the text below.
(a) Pole-zero plot in the z-plane. Horizontal axis labelled Re, vertical axis labelled Im. Legend: circle = zeroes, cross = poles. Zeroes (circles) at Re = -1/2 and Re = -1/4 on the negative real axis. Poles (crosses) at radius r = 1/sqrt(2) and angles +/- pi/4, i.e. at 1/4 + j1/4 and 1/4 - j1/4, plus a pole at Re = 1/2 on the positive real axis. Dashed lines from origin at angle pi/4 and -pi/4 to the complex poles.
(b) A two-stage transistor amplifier circuit diagram. The power supply is V_CC = 12 V connected to the top rail, and the bottom rail is grounded. The circuit consists of two NPN transistors, T1 and T2, connected in a cascade configuration.
Input Stage (T1): The input signal is applied to the base of T1 through a coupling capacitor C1 (10 uF). The base of T1 is connected to a biasing network consisting of resistor R1 (9.1 K) connected to V_CC and resistor R3 (36 K) connected to the emitter of T1. The emitter of T1 is connected to a voltage divider formed by resistor R5 (200 E) and resistor R6 (1.3 K) connected to ground. A bypass capacitor C4 (3.3 uF) is connected in parallel with R6. The collector of T1 is connected to the base of T2.
Output Stage (T2): The collector of T2 is connected to V_CC through a collector resistor R2 (2 K). The emitter of T2 is connected to ground through an emitter resistor R7 (1 K). A bypass capacitor C5 (100 uF) is connected in parallel with R7. The base of T2 is connected to the collector of T1 and also to a resistor R4 (100 K) which connects to the emitter of T1. The output signal is taken from the collector of T2 through a coupling capacitor C3 (100 uF) to a load resistor R_L (10 K) connected to ground. A capacitor C2 (10 uF) is connected between the collector of T1 and the base of T2.
(c) A pole-zero plot on the complex z-plane. The horizontal axis is labeled 'Re' and the vertical axis is labeled 'Im'. Zeros (marked with circles containing a plus sign) are located at -1/2 and -1/4 on the real axis. Poles (marked with crosses) are located at 1/2 on the real axis, and at two complex conjugate locations. The complex poles are located at a radius r = 1/sqrt(2) from the origin, at an angle of pi/4 and -pi/4 relative to the positive real axis. A legend indicates that circles represent zeros and crosses represent poles.
(d) No figure; text-only question asking to design a sequential circuit with two D flip-flops A and B and one input X, with state transitions 00 to 10 to 11 to 01 and repeat when X=1, and no change when X=0.
Model answer
Written by UPSC Answer Check against this question's marking rubric, to the expected length. UPSC does not publish answers for Mains — this is one way to score well, not an official key.
(a)
- Method: Shannon expansion for a 4-to-1 multiplexer. Take A as the most significant select line and B as the least significant select line. Then F = A′B′I₀ + A′B I₁ + AB′I₂ + AB I₃.
- For AB = 00, the relevant minterms are m₀, m₁, m₂, m₃. From the given list, m₁ and m₃ are 1, while m₀ and m₂ are 0. In C,D order 00, 01, 10, 11 this is 0, 1, 0, 1, so I₀ = C′D + CD = D.
- For AB = 01, the relevant minterms are m₄, m₅, m₆, m₇. Only m₄ is 1. In C,D order this is 1, 0, 0, 0, so I₁ = C′D′.
- For AB = 10, the relevant minterms are m₈, m₉, m₁₀, m₁₁. Only m₁₁ is 1. In C,D order this is 0, 0, 0, 1, so I₂ = CD.
- For AB = 11, the relevant minterms are m₁₂, m₁₃, m₁₄, m₁₅. All four are 1, so I₃ = 1.
- Verification: A′B′D gives m₁ + m₃; A′BC′D′ gives m₄; AB′CD gives m₁₁; AB gives m₁₂ + m₁₃ + m₁₄ + m₁₅. This reproduces the original sum of minterms.
- External gates: D goes directly to I₀; C′ and D′ are formed by inverters and ANDed for I₁; C and D are ANDed for I₂; I₃ is tied to logic 1. The MUX select lines are A and B. Final MUX data inputs: I₀ = D, I₁ = C′D′, I₂ = CD, I₃ = 1.
[(b)] The figure printed on the original question paper for this part could not be recovered from the scan, so this part is not answered here.
(c)
- Method: support of discrete convolution. The output is y(n) = Σ x(k) h(n-k).
- A term can be nonzero only when x(k) is nonzero and h(n-k) is nonzero. The given supports are N₂ ≤ k ≤ N₃ and N₀ ≤ n-k ≤ N₁.
- The second condition is equivalent to n-N₁ ≤ k ≤ n-N₀. Hence a nonzero term requires the intersection [N₂, N₃] ∩ [n-N₁, n-N₀] to be non-empty.
- Non-emptiness requires both N₂ ≤ n-N₀ and n-N₁ ≤ N₃. These give n ≥ N₀ + N₂ and n ≤ N₁ + N₃.
- Conversely, for any integer n satisfying N₀+N₂ ≤ n ≤ N₁+N₃, choose k = max(N₂, n-N₁). This k also satisfies k ≤ N₃ and k ≤ n-N₀, so at least one convolution term lies inside both supports. Thus the output can exist throughout the whole interval.
- Therefore, assuming N₀ ≤ N₁ and N₂ ≤ N₃, the output interval is N₀ + N₂ ≤ n ≤ N₁ + N₃.
- If either input or impulse-response interval is empty, the output is empty; if endpoint values are zero, the actual nonzero support may be a subinterval, but the possible output interval is the one above.
What "Solve" is asking you to do
Choose the method, then carry it through to a final answer. Identifying what kind of problem this is and why that method applies is the first thing marked; a correct figure arrived at invisibly earns almost nothing.
Structure that answers it
Given data and what is required → method chosen, with the reason it applies → set-up (equation, circuit, free body, trial balance) → working, step by step → answer with units and any condition of validity
Where marks are lost
Doing the middle steps mentally and writing only the result. In mathematics papers, a further loss comes from giving a decimal where the exact value in surds or fractions was wanted, or from skipping the justification a part explicitly asks for.
How this answer will be evaluated
Approach
(a) calculate: given > formula > substitution > result with units > interpretation | (b(i)) calculate: given > formula > substitution > result with units > interpretation | (b(ii)) calculate: given > formula > substitution > result with units > interpretation | (c) derive: given > assumptions > stepwise derivation > result > check Full marks: Complete derivations with correct circuit diagrams and final values.
Key points expected
- Truth table or K-map for F(A,B,C,D)
- Derivation of I0, I1, I2, I3 functions of C,D
- Labeled 4-to-1 MUX circuit diagram
- External gate logic for data inputs
- Small-signal equivalent circuit (h-parameter or rπ)
- Calculation of rπ and gm using β=499
- Impedance of coupling capacitors at 20 Hz
- Final gain values with units
Evaluation rubric
Each sub-part is marked on its own, against the marks and word limit printed on the paper.
- (a) Implementation of F(A,B,C,D) using a 4-to-1 MUX with A,B as select lines. 20 marks
calculate— given → formula → substitution → result with units → interpretation
Must cover
- Truth table or K-map for F(A,B,C,D)
- Derivation of I0, I1, I2, I3 functions of C,D
- Labeled 4-to-1 MUX circuit diagram
- External gate logic for data inputs
Loses marks
- Incorrect mapping of minterms to select lines
- Missing external gate logic for data inputs
Earns more
- Simplification of data input expressions
- Verification of output for all minterms
Extra mark
- Alternative implementation using NAND gates
- (b(i)) Small signal AC voltage gain at 20 Hz and 2 kHz.
calculate— given → formula → substitution → result with units → interpretation
Must cover
- Small-signal equivalent circuit (h-parameter or rπ)
- Calculation of rπ and gm using β=499
- Impedance of coupling capacitors at 20 Hz
- Final gain values with units
Loses marks
- Ignoring capacitive reactance at 20 Hz
- Using DC values for AC analysis
Earns more
- Explicit calculation of low-frequency cutoff
- Comparison of gain at 20 Hz vs 2 kHz
Extra mark
- Bode plot sketch of frequency response
- (b(ii)) DC voltages on collectors of T1 and T2.
calculate— given → formula → substitution → result with units → interpretation
Must cover
- DC bias analysis (capacitors open)
- Calculation of base currents and voltages
- KVL application for collector-emitter loops
- Final Vc1 and Vc2 values
Loses marks
- Ignoring base current in voltage divider
- Incorrect KVL loop equations
Earns more
- Verification of active region operation
- Step-by-step current calculation
Extra mark
- Power dissipation calculation
- (c) Interval for output y(n) in terms of N0, N1, N2, N3. 10 marks
derive— given → assumptions → stepwise derivation → result → check
Must cover
- Convolution sum definition y(n) = Σ x(k)h(n-k)
- Determination of non-zero limits for k
- Derivation of lower bound N0+N2
- Derivation of upper bound N1+N3
Loses marks
- Incorrect limits of summation
- Confusing input and impulse response intervals
Earns more
- Graphical representation of signal overlap
- Explanation of support of the convolution
Extra mark
- Example with specific integer values
Practice this exact question
Write your answer and it is marked point by point against the model answer above — what you covered, what you missed, what you got wrong.
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