(a) Design a Programmable Logic Array (PLA) for a combinational logic circuit that computes the square of 3-bit binary numbers…

(a) PLA to square a 3-bit binary number (20 marks)

Truth table. The input is A₂A₁A₀ (0 to 7) and the output is its square, at most 49, so six output bits B₅B₄B₃B₂B₁B₀ are needed.

• 000 (0) → 000000
• 001 (1) → 000001
• 010 (2) → 000100
• 011 (3) → 001001
• 100 (4) → 010000
• 101 (5) → 011001
• 110 (6) → 100100
• 111 (7) → 110001

Minimisation of each output (from the columns of the table):

• B₀ = 1 for 001, 011, 101, 111, so B₀ = A₀.
• B₁ = 0 for all inputs, so B₁ = 0 (its OR-plane line is left unconnected).
• B₂ = 1 for 010 and 110, so B₂ = A₁A₀′.
• B₃ = 1 for 011 and 101, so B₃ = A₂′A₁A₀ + A₂A₁′A₀ (= A₀(A₂ ⊕ A₁)); the two minterms cannot be combined.
• B₄ = 1 for 100, 101 and 111; the pairs (100, 101) and (101, 111) give B₄ = A₂A₁′ + A₂A₀.
• B₅ = 1 for 110 and 111, so B₅ = A₂A₁.

Minimum number of product terms. The distinct product terms are A₀, A₁A₀′, A₂′A₁A₀, A₂A₁′A₀, A₂A₁′, A₂A₀ and A₂A₁. No term is shared between outputs, and none can be removed, so the minimum is 7 product terms (6 if the output B₀ is wired directly from the input A₀ without using an AND-plane line).

PLA programming table (inputs: 1 = true, 0 = complemented, − = not connected; outputs: 1 = term connected to the OR gate of that output, − = not connected):

• P1: A₂ −, A₁ −, A₀ 1 → B₀ = 1
• P2: A₂ −, A₁ 1, A₀ 0 → B₂ = 1
• P3: A₂ 0, A₁ 1, A₀ 1 → B₃ = 1
• P4: A₂ 1, A₁ 0, A₀ 1 → B₃ = 1
• P5: A₂ 1, A₁ 0, A₀ − → B₄ = 1
• P6: A₂ 1, A₁ −, A₀ 1 → B₄ = 1
• P7: A₂ 1, A₁ 1, A₀ − → B₅ = 1

All other entries of the output columns (and the whole B₁ column) are unprogrammed. The PLA has 3 inputs, 7 product terms and 6 outputs (a 3 × 7 × 6 array, or 3 × 7 × 5 when the constant B₁ is dropped). Check: input 101 selects P1, P4, P5 and P6 and gives B₀ = 1, B₃ = 1, B₄ = 1, that is 011001 = 25.

(b)(i) Voltages across the SCR (10 marks)

The supply peak is V_m = 230√2 = 325.3 V. While the SCR is off the load current is zero, so the load voltage equals the back emf E and the SCR voltage is v_SCR = v_s − E = V_m sin ωt − E.

1. At the instant of triggering, ωt = α = 25°. Just before firing, v_s = 325.3 sin 25° = 137.5 V, so v_SCR = 137.5 − 120 = 17.5 V (forward). Since 17.5 V > 0 the SCR is forward biased (α exceeds sin⁻¹(120/325.3) = 21.6°), and it drops to about 0 V once it conducts.
2. When the current decays to zero, ωt = β = 220°. v_s = 325.3 sin 220° = −209.1 V, and the SCR is then reverse biased by v_SCR = −209.1 − 120 = −329.1 V.
3. Peak inverse voltage. After extinction the SCR voltage is v_s − E, which is most negative when v_s = −V_m (ωt = 270°, which lies after β = 220°): PIV = V_m + E = 325.3 + 120 = 445.3 V.

(b)(ii) Maximum freewheeling-diode current of a type-A chopper (10 marks)

Model. A type-A (step-down) chopper with duty ratio δ = T_on/T applies V_s to the R–L–E load while the chopper is on and lets the load current freewheel through the diode while it is off. In continuous conduction, and assuming a small current ripple (the load current is essentially constant at its mean I_a), the output voltage is V_o = δV_s. The average voltage across L is zero, so

I_a = (δV_s − E)/R.

The diode carries the load current for the off-time (1 − δ)T, so its average current is

I_fd = (1 − δ) I_a = (1 − δ)(δV_s − E)/R.

Maximisation over δ. Differentiate:

dI_fd/dδ = (1/R)[−(δV_s − E) + (1 − δ)V_s] = (1/R)[V_s + E − 2δV_s] = 0, so δ = ½(1 + E/V_s).

The second derivative is −2V_s/R < 0, so this is a maximum. The value δ = ½(1 + E/V_s) lies between E/V_s and 1 for E ≤ V_s, so the load current is positive and the assumptions hold. At this δ:

• 1 − δ = ½(1 − E/V_s);
• δV_s − E = ½(V_s + E) − E = ½(V_s − E) = (V_s/2)(1 − E/V_s).

Therefore

I_fd,max = (1/R) × ½(1 − E/V_s) × (V_s/2)(1 − E/V_s) = (V_s/4R)(1 − E/V_s)²,

as required.

(c) Relation between k_p and k_f for equal maximum phase (10 marks)

The message is m(t) = t for 0 ≤ t ≤ 1, 1 for 1 ≤ t ≤ 2, −1 for 2 ≤ t ≤ 3, and 0 otherwise.

Phase modulation. The phase follows the message: φ_PM(t) = k_p m(t). Its maximum is k_p max|m(t)| = k_p × 1 = k_p.

Frequency modulation. The instantaneous frequency is f_i = f_c + k_f m(t), so the phase is the integral of the message:

φ_FM(t) = 2π k_f ∫₀ᵗ m(τ) dτ.

The integral is t²/2 for 0 ≤ t ≤ 1 (reaching 0.5), 0.5 + (t − 1) for 1 ≤ t ≤ 2 (reaching 1.5), 1.5 − (t − 2) for 2 ≤ t ≤ 3 (falling to 0.5), and stays at 0.5 afterwards. So max|∫m| = 1.5, at t = 2 s, and the maximum FM phase is 2π k_f × 1.5 = 3π k_f.

Condition. Equal maximum phase requires k_p = 3π k_f, that is k_p ≈ 9.42 k_f, with k_f in Hz per unit of m(t) and k_p in rad per unit of m(t). (If k_f were defined in rad/s per unit, φ_FM = k_f ∫m and the condition would be k_p = 1.5 k_f.)