(a) A unity feedback system has open loop transfer function G(s) = K/(s(s+q)). Evaluate the value of K and q so that settling…

(a) Design of K and q for given settling time and overshoot (10 marks)

The closed loop of the unity-feedback system is T(s) = K/(s² + qs + K), which compares with the standard form ω_n²/(s² + 2ζω_n s + ω_n²), so

ω_n² = K and 2ζω_n = q.

Damping ratio from the peak overshoot. M_p = e^(−πζ/√(1 − ζ²)) = 0.20, so πζ/√(1 − ζ²) = ln 5 = 1.609, that is ζ² = 1.609²/(π² + 1.609²) = 2.590/12.460 = 0.2079 and ζ = 0.456.

Natural frequency from the settling time. For the 2% band, t_s = 4/(ζω_n) = 6 s, so ζω_n = 0.667 and ω_n = 0.667/0.456 = 1.46 rad/s.

Gain and pole. K = ω_n² = 1.462² = 2.14 and q = 2ζω_n = 2 × 0.667 = 1.33.

So G(s) = 2.14/[s(s + 1.33)]. (With the 5% band, t_s = 3/(ζω_n), the values would be ω_n = 1.10 rad/s, K = 1.20 and q = 1.0.)

(b) 8085 routine (10 marks)

• MVI B, 0FH: B = 0FH.
• MVI C, ABH: C = ABH.
• MOV A, C: A = ABH.
• ADD B: A = ABH + 0FH = BAH (no carry, so CY = 0).
• SBI 02H: subtract immediate with borrow, A = A − 02H − CY = BAH − 02H − 0 = B8H.
• STA 00FFH: stores the accumulator in memory location 00FFH.

The value stored at 00FFH is B8H.

Flags after the last arithmetic instruction (SBI; STA does not change the flags). The result is B8H = 1011 1000:

• S = 1 (bit 7 of the result is 1);
• Z = 0 (the result is not zero);
• P = 1 (the result has four 1 bits, even parity);
• CY = 0 (no borrow, since BAH is larger than 02H);
• AC = 1 (in the 8085 subtraction is done by adding the 2's complement, and the low nibble A + D + 1 = 18H produces a carry out of bit 3, meaning no borrow from the low nibble).

(c) Probable error in a resistance from voltmeter and ammeter readings (10 marks)

R = V/I = 500/15 = 33.3 Ω. For a quotient the probable errors combine by the root-sum-square law, since probable errors are independent and do not all reach their limits at once:

ΔR/R = √[(ΔV/V)² + (ΔI/I)²].

The relative errors are ΔV/V = 20/500 = 0.04 (4%) and ΔI/I = 3/15 = 0.20 (20%). Therefore

ΔR/R = √(0.04² + 0.20²) = √0.0416 = 0.204, that is ±20.4%,

and ΔR = 0.204 × 33.3 = ±6.8 Ω. The resistance is R = 33.3 ± 6.8 Ω. (The worst-case, or limiting, error would be the arithmetic sum 4% + 20% = 24%, or 8 Ω, but a probable error uses the root-sum-square.) The ammeter error dominates.

(d) Saturated-reactor compensator (10 marks)

Principle. A saturated reactor is a reactor whose iron core is deliberately worked in the saturation region of its magnetising characteristic. Below the knee the flux is nearly proportional to the voltage and the current is small. Above the knee a small rise in voltage produces a large rise in current, since the incremental reactance falls to that of the air-core winding. So the voltage across the reactor is held almost constant while the current changes widely: it draws more inductive current, and absorbs more reactive power, as the bus voltage rises, and less as it falls, without any control system.

Circuit. The reactor is connected to the bus through a transformer, in parallel with a fixed shunt capacitor bank, and with a series slope-correcting capacitor. The capacitor supplies reactive power when the system voltage is low, when the reactor draws almost no current, and the reactor absorbs the excess as the voltage rises. The net effect is a compensator that regulates the bus voltage over a wide range of reactive demand.

V–I characteristic and its slope. The characteristic is linear up to the knee at about 1.0 pu and then rises with a small slope (the saturated reactance, typically 8–15% of the base without correction). The slope means the voltage changes slightly with the compensator current, so regulation is not perfect.

Obtaining a lower slope. The slope is reduced by a series slope-correcting capacitor, whose voltage drop opposes the reactor's inductive rise in the saturated region. Tuning this compensation can bring the slope down to about 2–5% or even to zero, and over-compensation gives a negative slope. The slope is the ratio of the voltage change to the current change, ΔV/ΔI.

Main features.

• It is passive and self-regulating: there are no thyristors, no firing circuits and no closed-loop control, so the response is almost instantaneous (within a cycle).
• The construction is robust, with no moving parts, high overload capacity and low maintenance.
• The saturating iron produces harmonics, which are reduced by a multi-core arrangement such as the twin-tripler or treble-tripler reactor with delta-connected windings.
• It needs a large mass of iron, is heavy and noisy, and has higher losses than a thyristor-controlled reactor.
• The voltage set point is fixed by the design (the knee of the characteristic), so it is inflexible compared with thyristor-based static var compensators.

(e) Discrete memoryless channel (10 marks)

(i) Channel diagram (5 marks). In the matrix, row i belongs to the input x_i and column j to the output y_j. From x₁ the output is y₁ with probability 1 − p and y₂ with probability p; from x₂ it is y₂ with probability p and y₃ with probability 1 − p. The other two entries are zero, so there are no transitions x₁ → y₃ and x₂ → y₁. This is a binary erasure channel with y₂ as the erasure symbol.

(ii) Output probabilities (5 marks). With equally likely inputs, P(x₁) = P(x₂) = 0.5, and p = 0.2, the output probabilities are P(y_j) = Σ_i P(x_i) P(y_j|x_i):

• P(y₁) = 0.5 × (1 − p) = 0.5 × 0.8 = 0.4;
• P(y₂) = 0.5 × p + 0.5 × p = 0.5 × 0.2 + 0.5 × 0.2 = 0.2;
• P(y₃) = 0.5 × (1 − p) = 0.4.

They add up to 1. The joint probabilities are P(x₁, y₁) = 0.4, P(x₁, y₂) = 0.1, P(x₂, y₂) = 0.1 and P(x₂, y₃) = 0.4. As a check, H(Y) = 1.522 bits and H(Y|X) = H(p) = 0.722 bits, so I(X; Y) = 0.80 bits = (1 − p) H(X).