(a) (i) A system has a unit response as c(t) = 1 − e^(−0·5t). Evaluate its unit impulse and unit ramp response, assuming zero…

(a)(i) Impulse and ramp response from the step response (10 marks)

The unit-step response is c(t) = 1 − e^(−0.5t), so C(s) = 1/s − 1/(s + 0.5) = 0.5/[s(s + 0.5)]. With R(s) = 1/s the transfer function is

G(s) = C(s)/R(s) = 0.5/(s + 0.5),

a first-order system with time constant T = 2 s and unit dc gain.

Unit impulse response. With R(s) = 1, C(s) = 0.5/(s + 0.5), so

g(t) = 0.5 e^(−0.5t), t ≥ 0 (the derivative of the step response).

Unit ramp response. With R(s) = 1/s², C(s) = 0.5/[s²(s + 0.5)] = 1/s² − 2/s + 2/(s + 0.5), so

c_r(t) = t − 2 + 2e^(−0.5t), t ≥ 0 (the integral of the step response).

Check: c_r(0) = 0 and c_r′(0) = 1 − 1 = 0. For large t the output follows t − 2, lagging the ramp by 2 s (the steady-state error equals the time constant, 2).

(a)(ii) Solution of the homogeneous state equation (10 marks)

The solution is x(t) = e^(At) x(0), where e^(At) = L⁻¹{(sI − A)⁻¹}.

State transition matrix. With A = [[0, 1], [−1, −2]],

sI − A = [[s, −1], [1, s + 2]], det = s(s + 2) + 1 = (s + 1)²,

so the characteristic equation has a repeated root s = −1. Then

(sI − A)⁻¹ = (1/(s + 1)²) [[s + 2, 1], [−1, s]] = [[1/(s + 1) + 1/(s + 1)², 1/(s + 1)²], [−1/(s + 1)², 1/(s + 1) − 1/(s + 1)²]].

Taking the inverse transform (L⁻¹{1/(s + 1)²} = te^(−t)):

e^(At) = e^(−t) [[1 + t, t], [−t, 1 − t]].

(Alternatively, A + I = N with N² = 0, so e^(At) = e^(−t)(I + Nt), which gives the same matrix.)

Solution for x(0) = [1, 0]ᵀ.

x(t) = e^(−t) [[1 + t, t], [−t, 1 − t]] [1, 0]ᵀ = e^(−t) [1 + t, −t]ᵀ,

that is x₁(t) = (1 + t)e^(−t) and x₂(t) = −t e^(−t).

Check: x₁(0) = 1, x₂(0) = 0, and ẋ₁ = e^(−t) − (1 + t)e^(−t) = −te^(−t) = x₂, as required by the first state equation. Both states decay to zero, so the system is asymptotically stable.

(b) Error of an electrodynamometer wattmeter with the pressure coil on the load side (20 marks)

Connection. The pressure coil (PC) is connected directly across the load, so it sees the load voltage V = 200 V, but the current coil (CC) carries the load current and the pressure-coil current together. The true load power is P = VI cos φ = 200 × 20 × 0.5 = 2000 W.

Pressure-coil data. R_p = 5000 Ω, X_p = 2πfL = 2π × 50 × 0.06 = 18.85 Ω. The PC current is I_p = V/|Z_p| = 200/5000.04 = 0.040 A, and it lags the voltage by β = tan⁻¹(X_p/R_p) = tan⁻¹(18.85/5000) = 0.216°.

(1) Error from the pressure-coil inductance. The PC current lags the voltage by β, so the wattmeter responds to the current I at an angle φ − β instead of φ. The reading for the load current alone is

W₁ = V I cos β cos(φ − β) = 200 × 20 × 0.99999 × cos(59.784°) = 2013.0 W.

The error is (2013.0 − 2000)/2000 = +0.65%, given by the factor cos²β(1 + tan φ tan β) = 1.0065, which is large here because tan 60° = 1.73 for a low-pf load.

(2) Error from the pressure-coil loss. Because the CC also carries the PC current, the reading includes the power taken by the pressure circuit, V²/R_p = 200²/5000 = 8 W (more exactly V I_p cos β = 8.0 W). The error from this is 8/2000 = +0.40%.

Total. The wattmeter reading is W = 2013.0 + 8.0 = 2021 W, so the percentage error is

(2021 − 2000)/2000 × 100 = +1.05% (the meter reads high).

Comment. The error is small, about 1%, because the pressure circuit has a high resistance and a small phase angle. It is positive for a lagging load and would be negative for a leading load, and it increases as the power factor falls (through tan φ). It can be removed by subtracting the pressure-coil loss and by compensating the coil inductance, for example with a small capacitor across part of the series resistance. The given current-coil resistance of 0.4 Ω is not part of this connection. If instead the pressure coil were connected on the supply side of the current coil, the voltage across the PC would include the CC drop, and the reading would exceed the load power by the CC loss, I²R_cc = 20² × 0.4 = 160 W, an error of +8%. For a high-current load like this one, the load-side connection is therefore better.

(c) 8085 interrupts, EI/DI and the SIM and RIM words (10 marks)

Types of interrupts. The 8085 has five hardware interrupts and eight software interrupts.

• TRAP (RST 4.5): non-maskable, highest priority, level and edge sensitive, vector 0024H.
• RST 7.5: maskable, rising-edge sensitive (latched), second priority, vector 003CH.
• RST 6.5: maskable, level sensitive, third priority, vector 0034H.
• RST 5.5: maskable, level sensitive, fourth priority, vector 002CH.
• INTR: maskable, level sensitive, lowest priority and non-vectored; the interrupting device supplies an instruction (normally RST n or CALL) after INTA.
• Software interrupts: the instructions RST 0 to RST 7, which branch to 8 × n (0000H, 0008H, …, 0038H). They cannot be masked.

The hardware interrupts other than INTR are vectored. Vectored interrupts jump to a fixed address, and non-vectored ones take the address from the device.

EI and DI. EI (enable interrupts, opcode FBH) sets the interrupt-enable flip-flop; the maskable interrupts (RST 7.5, 6.5, 5.5, INTR) are then recognised after the following instruction has been executed. DI (disable interrupts, opcode F3H) resets the flip-flop and disables all the maskable interrupts; TRAP is unaffected. The flip-flop is also reset by RESET and automatically when an interrupt is accepted. DI is used around critical or time-critical code sections that must not be interrupted, and EI is used to re-enable interrupts, usually just before RET at the end of a service routine so that interrupts can be accepted again once the routine has returned.

SIM (set interrupt mask) – accumulator bits.

• D₀ (M5.5), D₁ (M6.5), D₂ (M7.5): mask bits; 1 masks (disables) the interrupt, and they take effect only if D₃ = 1.
• D₃ (MSE): mask set enable; 1 allows D₀–D₂ to set the masks.
• D₄ (R7.5): reset RST 7.5 flip-flop; 1 clears the latched request.
• D₅: not used.
• D₆ (SOE): serial output enable; 1 lets D₇ appear on SOD.
• D₇ (SOD): serial output data bit sent to the SOD pin.

RIM (read interrupt mask) – accumulator bits after execution.

• D₀ (M5.5), D₁ (M6.5), D₂ (M7.5): current mask status (1 = masked).
• D₃ (IE): interrupt-enable flip-flop status (1 = enabled).
• D₄ (I5.5), D₅ (I6.5), D₆ (I7.5): pending status of the respective interrupts (1 = pending).
• D₇ (SID): serial input data bit read from the SID pin.