(a) Determine the response of the system shown in the following figure when it is excited by a unit step input. (20 marks) (b)…

(a) Step response of the unity-feedback system (20 marks)

The forward path is G(s) = (s + 1) × 2/s² = 2(s + 1)/s², with unity negative feedback (H = 1). The closed-loop transfer function is

C(s)/R(s) = G/(1 + G) = 2(s + 1)/(s² + 2s + 2).

Comparing the denominator with s² + 2ζω_n s + ω_n²: ω_n = √2 = 1.414 rad/s and ζ = 1/√2 = 0.707, so the system is under-damped, with a zero at s = −1 and poles at s = −1 ± j1.

For a unit step, R(s) = 1/s, so

C(s) = 2(s + 1)/[s(s² + 2s + 2)] = A/s + (Bs + D)/(s² + 2s + 2).

Then A = 2(1)/2 = 1, and equating coefficients of 2(s + 1) = (s² + 2s + 2) + (Bs + D)s gives B = −1 and D = 0. Hence

C(s) = 1/s − s/[(s + 1)² + 1] = 1/s − (s + 1)/[(s + 1)² + 1] + 1/[(s + 1)² + 1].

Taking the inverse Laplace transform:

c(t) = 1 − e^(−t) cos t + e^(−t) sin t = 1 + e^(−t)(sin t − cos t), for t ≥ 0.

Checks. c(0) = 1 + (0 − 1) = 0, and the final value is c(∞) = 1, so the steady-state error to a unit step is zero. The derivative is c′(t) = 2e^(−t) cos t, which is zero at t = π/2 = 1.571 s. Hence the peak time is t_p = 1.571 s and the peak value is c(t_p) = 1 + e^(−π/2) = 1.208, a peak overshoot of 20.8%. The settling time (2% band) is about 4/(ζω_n) = 4/1 = 4 s, and the response is oscillatory, decaying with the envelope e^(−t).

(b)(i) 8085 pins and the internal registers (10 marks)

1. READY (input). A slow memory or peripheral pulls READY low to say that it is not ready to send or accept data. The microprocessor samples it in T₂ of a read or write cycle and, if it is low, inserts wait states until it goes high, which lets fast processors work with slow devices.
2. SID (serial input data, input). A serial data line. The bit present on SID is loaded into bit 7 of the accumulator when the RIM instruction is executed.
3. SOD (serial output data, output). A serial data line. When the SIM instruction is executed with the serial-output enable bit (D₆) set, bit 7 of the accumulator is latched to SOD.
4. INTR (interrupt request, input). A general-purpose, maskable, non-vectored, level-sensitive interrupt. It is sampled in the last T-state of each instruction, and it is recognised only if interrupts are enabled (EI). The processor then issues INTA and the device supplies an instruction, normally RST n or CALL, to which the processor branches.
5. CLK (OUT), output. The system clock output, at half the frequency of the crystal or LC circuit on X₁ and X₂ (3 MHz for a 6 MHz crystal). It drives clock inputs of peripherals and synchronises the system.

Instruction decoder. The opcode fetched in the opcode-fetch cycle is held in the instruction register and decoded by the instruction decoder. The decoder, with the timing and control unit, decides the machine cycles and the control signals (RD, WR, ALE, IO/M, S₀, S₁) needed to execute the instruction.

Stack pointer (SP). A 16-bit register that points to the top of the stack, a last-in first-out area of read/write memory. It is decremented by 2 on PUSH or CALL, when data or the return address are saved, and incremented by 2 on POP or RET. It is also used to save the program counter when an interrupt is accepted.

Program counter (PC). A 16-bit register that holds the address of the next instruction to be fetched. It is incremented automatically after each byte is fetched, so the program is executed sequentially, and it is loaded with a new address by jump, call, return and interrupt operations. The 8085 can address 64 KB of memory through the PC.

(b)(ii) Timing diagram for MVI B, 05H (10 marks)

MVI B, 05H is a two-byte instruction: the opcode (06H, written XXH as instructed) at 220AH and the data 05H at 220BH. It needs two machine cycles and seven T-states:

• M₁, opcode fetch (T₁ to T₄). In T₁ the processor places 22H on A₁₅–A₈ and 0AH on AD₇–AD₀, and ALE goes high in T₁ so that an external latch can hold the low-order address. IO/M = 0 (memory access; RD and WR are active low), and the status signals are S₁S₀ = 11 (opcode fetch). RD goes low from T₂ to T₃ and the memory places the opcode on AD₇–AD₀, which the processor latches at the end of T₃. In T₄ the opcode is decoded; RD is high and WR remains high.
• M₂, memory read (T₁ to T₃). The PC now holds 220BH. In T₁ the address 22H, 0BH appears on the buses with ALE high, IO/M = 0 and S₁S₀ = 10 (memory read). RD is low in T₂ and T₃, and the data byte 05H is placed on AD₇–AD₀ and read into register B at the end of T₃.

READY is held high (no wait state) and WR stays high (inactive) throughout, since there is no write.

(c) Loading error of voltmeters (10 marks)

Input resistances. Each voltmeter's resistance is its sensitivity times its range: V₁ = 2000 Ω/V × 100 V = 200 kΩ, and V₂ = 30 000 Ω/V × 100 V = 3 MΩ.

True voltage without a meter. The 150 kΩ resistor with the 300 kΩ series resistor across the 200 V source has V = 200 × 150/(300 + 150) = 66.67 V.

Reading of V₁. The meter is in parallel with the 150 kΩ resistor: R_p = 150 × 200/(150 + 200) = 85.71 kΩ. Then

V₁ = 200 × 85.71/(300 + 85.71) = 44.4 V.

Reading of V₂. R_p = 150 × 3000/(150 + 3000) = 142.86 kΩ, so

V₂ = 200 × 142.86/(300 + 142.86) = 64.5 V.

The loading error is (44.4 − 66.7)/66.7 = −33.3% for V₁ and (64.5 − 66.7)/66.7 = −3.2% for V₂, which shows that a high-sensitivity meter is needed for a high-resistance circuit.