Q1 50M Compulsory solve Network analysis, signals, DC machines, transistors, digital logic
(a) In Figure 1(a) shown below, the two-port network is characterized in terms of y-parameters with y₁₁ = 3·3 × 10⁻³ S, y₂₂ = 5 × 10⁻³ S and y₁₂ = y₂₁ = 0. Find the voltage across 200 Ω load. (10 marks)
(b) For the signal shown in Figure 1(b), calculate the total energy of the signal X(t). Also sketch y(t) = X(10t – 5). (10 marks)
(c) A 220 V dc shunt motor has armature resistance Rₐ = 0·13 Ω, field resistance Rf = 250 Ω and rotational loss 230 W. On full-load, the line current is 9·5 A with the motor running at 1440 rpm. Determine the following:
(i) The mechanical power developed
(ii) The power output
(iii) The load torque
(iv) The full-load efficiency (10 marks)
(d) For the transistor circuit shown in Figure 1(d), determine the value of reverse saturation current, I_S, that would give a collector current of 1 mA, if β = 80, V_A = ∞ and V_T = 26 mV at T = 300 K. (10 marks)
(e) Consider the four variables logic function defined as follows:
F (A, B, C, D) = ĀC + ĀD + B̄C + B̄D + ABC̄ D̄
Assuming input variables as A, B, C and D, propose a logic circuit using only three logic gates to implement the function. (10 marks)
हिंदी में पढ़ें
(a) चित्र 1(a) में प्रदर्शित द्वि-प्रद्वार जालक्रम के, y-प्राचलों y₁₁ = 3·3 × 10⁻³ S, y₂₂ = 5 × 10⁻³ S तथा y₁₂ = y₂₁ = 0 के रूप में लक्षण बताए गए हैं । 200 Ω भार के आर-पार वोल्टता का मान ज्ञात कीजिए । (10 अंक)
(b) चित्र 1(b) में प्रदर्शित संकेत के लिए, संकेत X(t) की संपूर्ण ऊर्जा की गणना कीजिए । y(t) = X(10t – 5) का आरेखण भी कीजिए । (10 अंक)
(c) एक 220 V dc समानान्तर क्रम मोटर का, आर्मेचर प्रतिरोध Rₐ = 0·13 Ω, क्षेत्र प्रतिरोध Rf = 250 Ω तथा घूर्णन हान 230 W है । मोटर के 1440 rpm पर पूर्ण भार पर चलते समय लाइन धारा का मान 9·5 A है । निम्नलिखित का मान ज्ञात कीजिए :
(i) विकसित (उत्पन्न) यांत्रिक शक्ति
(ii) निर्गत शक्ति
(iii) भार (लोड) बल-आघूर्ण
(iv) पूर्ण भार दक्षता (10 अंक)
(d) चित्र 1(d) में प्रदर्शित ट्रांजिस्टर परिपथ के लिए, व्युत्क्रम संतृप्त धारा I_S का वह मान ज्ञात कीजिए जो संग्राहक धारा का मान 1 mA कर दे, यदि T = 300 K पर β = 80, V_A = ∞ तथा V_T = 26 mV हो । (10 अंक)
(e) निम्नानुसार परिभाषित चतुर्वर तार्किक फलन पर विचार कीजिए :
F (A, B, C, D) = ĀC + ĀD + B̄C + B̄D + ABC̄ D̄
A, B, C और D को निवेश चर मानकर केवल तीन तार्किक द्वारों का प्रयोग करते हुए इस फलन के कार्यान्वयन के लिए तार्किक परिपथ प्रस्तावित कीजिए । (10 अंक)
Answer approach & key points
(a) calculate: given > formula > substitution > result with units > interpretation | (b) calculate: given > formula > substitution > result with units > interpretation | (c) calculate: given > formula > substitution > result with units > interpretation | (d) calculate: given > formula > substitution > result with units > interpretation | (e) describe: define > structure or process in order > labelled diagram > significance Full marks: Rigorous method, correct units, all sub-parts fully solved with clear diagrams.
- Recognise that the 0.01 F capacitor carries I₁ + I₂, with X_C = 50 Ω and jωL = j4 Ω at ω = 2.
- Write the two loop equations using V₁ = I₁/y₁₁ and V₂ = I₂/y₂₂ and solve them.
- State the load voltage as about 7.94 V peak with phase about −74.6°.
- Read the waveform correctly and integrate X² piecewise to get E = 32/3.
- Apply y(t) = X(10t − 5): compression by 10 and centring at t = 0.5, with breakpoints 0.2, 0.3, 0.4, 0.6, 0.7, 0.8.
- Sketch with levels 0, 1, 2, 1, 0 and labelled axes.
- Find I_f = 0.88 A and I_a = 8.62 A.
- Developed power E_b I_a = 1886.7 W and output = 1886.7 − 230 = 1656.7 W.
- Torque = P_out/ω = 10.99 N·m and efficiency = 1656.7/2090 = 79.3%.
- Identify the transistor as PNP, with the base returned to the collector node through 20 kΩ.
- Find I_B = 12.5 μA, V_C = 1.62 V, V_B = 1.87 V and V_EB = 0.63 V (1.6 kΩ carries I_C + I_B).
- Use I_C = I_S exp(V_EB/V_T) to get I_S ≈ 3 × 10⁻¹⁴ A.
- Simplify F to (AB)′(C + D) + AB(C + D)′.
- Recognise F = (A·B) ⊕ (C + D).
- Implement with one AND, one OR and one XOR gate and verify.
Q2 50M solve Thevenin's theorem, convolution, sequential circuits
(a) Find the Thevenin's equivalent of the circuit shown in Figure 2(a) below as seen from the load impedance Z_L. Also find the value of Z_L for maximum power transfer. (20 marks)
(b) (i) Compute the convolution X[n] * h[n], where
X[n] = (1/2)^(-n) u[-n-2]
h[n] = u[n-2].
(ii) Consider the signal X(t) shown in Figure 2(b)(ii) below. Represent the signal X(t) in terms of rectangular pulse signal V(t) shown in the same figure. (20 marks)
(c) Consider the circuit shown in Figure 2(c) below. Let inputs A, B and C be all initially LOW. Output Y is supposed to go HIGH only when A, B and C go HIGH in a certain sequence. Determine the sequence that will make Y go HIGH. Modify this circuit to use D-Flip-flops. (10 marks)
हिंदी में पढ़ें
(a) चित्र 2(a) में प्रदर्शित परिपथ का, भार प्रतिबाधा Z_L से दृश्य थेवेनिन समतुल्य ज्ञात कीजिए। अधिकतम शक्ति अंतरण के लिए Z_L का मान भी ज्ञात कीजिए। (20 अंक)
(b) (i) संवलन (कनवोल्यूशन) X[n] * h[n] की गणना कीजिए, जहाँ
X[n] = (1/2)^(-n) u[-n - 2]
h[n] = u[n - 2].
(ii) चित्र 2(b)(ii) में प्रदर्शित संकेत X(t) पर विचार कीजिए । उसी चित्र में प्रदर्शित आयताकार स्पंद संकेत V(t) के सापेक्ष संकेत X(t) का निरूपण कीजिए । (20 अंक)
(c) चित्र 2(c) में प्रदर्शित परिपथ पर विचार कीजिए । माना कि प्रारंभ में निवेश A, B और C सभी निम्न (लो) हैं । A, B और C के किसी एक विशेष प्रक्रम में उच्च (हाई) होने पर निर्गत Y का उच्च होना अपेक्षित है । उस प्रक्रम को ज्ञात कीजिए जो Y को उच्च स्तर पर ले जाएगा । इस परिपथ को D-फ्लिप-फ्लॉपों का प्रयोग करने के लिए परिवर्तित कीजिए । (10 अंक)
Answer approach & key points
(a) calculate: given > formula > substitution > result with units > interpretation | (b) calculate: given > formula > substitution > result with units > interpretation | (c) describe: define > structure or process in order > labelled diagram > significance Full marks: Complete working with correct equivalent circuits, accurate calculations, and clear diagrams for all parts
- Handle the coupling correctly: jωM = j3 Ω, dots at the top, (2 + j3) Ω branch carrying I₁ + I₂.
- Obtain V_th = 100(2 + j6)/(2 + j5) ≈ 117.4∠3.4° V and Z_th = (2 + j198)/29 ≈ 0.069 + j6.83 Ω.
- State Z_L = Z_th* ≈ 0.069 − j6.83 Ω for maximum power transfer.
- Write the convolution sum with limits k ≤ min(−2, n − 2) and sum the geometric series to get y[n] = 2^(n−1) for n ≤ 0 and 1/2 for n ≥ 0.
- Handle the step functions u[−n − 2] and u[n − 2] correctly.
- Give X(t) = V(t − 1) + V(t − 2) + 2V(t − 3) with the shifts and amplitudes checked interval by interval.
- Show Q⁺ = J + Q for each JK stage with K = 0 and deduce the sequence A, then B, then C.
- Convert using D = JQ̄ + K̄Q = J + Q.
- Give D_X = A + X clocked by B and D_Y = X + Y clocked by C, with the clear tied to Start.
Q3 50M calculate Analog circuits and signal processing
(a) (i) Explain what happens when a circuit shown in Figure 3(a)(i) below is constructed using logarithmic amplifier. 10
Figure 3(a)(i)
(ii) Explain what happens if the topology is modified as shown in Figure 3(a)(ii) below. 10
Figure 3(a)(ii)
(b) For the circuit shown in Figure 3(b), calculate the voltage V₀(t) as function of time,
Figure 3(b)
where V(t) = 10 sin (6t + 60°) V and I(t) = 5 cos (4t + 30°) A. 20
(c) A mixer (analog multiplier) is used as a process in some analog communication systems. Two signals X₁(t) and X₂(t) are mixed to produce the output y(t) = X₁(t) X₂(t).
If X₁(t) = 10 sin c (10t) and X₂(t) = 2 cos (1000 πt), then calculate and plot the magnitude of the Fourier transform of output signal. Further, specify and prove the property of Fourier transform used in calculations. 10
हिंदी में पढ़ें
(a) (i) समझाइए कि जब चित्र 3(a)(i) में प्रदर्शित परिपथ को लघुगणकीय प्रवर्धक का प्रयोग करते हुए निर्मित किया जाएगा, तो क्या होगा ।
चित्र 3(a)(i)
(ii) समझाइए कि यदि संस्थितिकी को चित्र 3(a)(ii) में दर्शाए अनुसार परिवर्तित कर दिया जाए, तो क्या होगा ।
चित्र 3(a)(ii)
(b) चित्र 3(b) में प्रदर्शित परिपथ के लिए वोल्टता V₀(t) की गणना समय के फलन के रूप में कीजिए,
चित्र 3(b)
जहाँ V(t) = 10 sin (6t + 60°) V और I(t) = 5 cos (4t + 30°) A हैं।
(c) एक मिश्रक (अनुकृप गुणक) को किसी अनुकृप संचार प्रणाली के एक प्रक्रम के रूप में प्रयुक्त किया गया है । निर्गत y(t) = X₁(t) X₂(t) निर्मित करने के लिए दो संकेतों X₁(t) तथा X₂(t) को मिश्रित किया गया है ।
यदि X₁(t) = 10 sin c (10t) तथा X₂(t) = 2 cos (1000 πt) हो, तो निर्गत संकेत के फुरिये रूपांतर के परिमाण की गणना कीजिए तथा उसका आरेखण कीजिए । गणना में प्रयुक्त फुरिये रूपांतर के गुणों का उल्लेख कीजिए तथा उन्हें सिद्ध कीजिए ।
Answer approach & key points
(a(i)) explain: definition/context > points in order > small example > short close | (a(ii)) explain: definition/context > points in order > small example > short close | (b) calculate: given > formula > substitution > result with units > interpretation | (c) calculate: given > formula > substitution > result with units > interpretation Full marks: All parts solved with correct method, clear steps, and proper interpretation.
- Show that Q₁ in the feedback with a virtual ground gives V₁ = −V_T ln(V_REF/(R₁I_S)).
- Find V_BE2 = V₁ + V_B and I_X = (R₁I_S²/V_REF) e^(V_B/V_T).
- Conclude that the circuit realises a reciprocal function, I_X ∝ 1/V_REF.
- Read the topology correctly: bases grounded, emitters at V₁, so V_BE1 = V_BE2 = −V₁.
- Derive I_X = (V_REF/R₁)(I_S2/I_S1), equal to V_REF/R₁ for matched devices.
- Identify a current mirror whose output is independent of the load while Q₂ is active.
- Use superposition, one source at a time, with the other sources suppressed.
- Write the nodal equations with jωC and 1/(jωL) at ω = 6 and ω = 4.
- Combine as V₀(t) = 20 + 1.763 cos(6t − 109.8°) + 14.20 cos(4t − 43.5°) V.
- Find X₁(ω) = π rect(ω/20) and X₂(ω) = 2π[δ(ω − 1000π) + δ(ω + 1000π)].
- State and prove F{x₁x₂} = (1/2π) X₁ * X₂ and obtain Y(ω) = π rect((ω − 1000π)/20) + π rect((ω + 1000π)/20).
- Plot two rectangles of height π and width 20 rad/s at ±1000π rad/s.
Q4 50M calculate Digital signal processing and digital electronics
(a) Consider a discrete time system with transfer function given by
H(z) = Y(z)/R(z) = (z⁻¹ - ½z⁻²)/(1 - z⁻¹ + 2/9 z⁻²).
Calculate the following :
(i) The impulse response of the system
(ii) The step response of the system with zero initial conditions
(iii) The step response of the system with initial conditions y[-1] = 1 and y[-2] = 2 20
(b) (i) Verify by determining the logic equation for the output and by constructing the truth table for the logic circuit shown in Figure 4(b).
(ii) Use an 8 to 1 multiplexer and logic gates to implement the following function :
F(A, B, C, D, E) = Σ m (0, 1, 2, 4, 5, 6, 7, 13, 14, 20, 21, ..., 28, 29, 30, 31)
20
Figure 4(b)
(c) Determine the closed loop gain of the inverting amplifier shown in Figure 4(c) below. Explain the result if R₁ → 0 or R₃ → 0.
10
हिंदी में पढ़ें
(a) H(z) = Y(z)/R(z) = (z⁻¹ - ½z⁻²)/(1 - z⁻¹ + 2/9 z⁻²) द्वारा प्रदर्शित अंतरण फलन वाले एक असतत समय तंत्र पर विचार कीजिए तथा निम्नलिखित की गणना कीजिए :
(i) तंत्र की आवेग अनुक्रिया
(ii) शून्य प्रारंभिक स्थिति के लिए तंत्र की पद अनुक्रिया
(iii) प्रारंभिक स्थिति y[-1] = 1 तथा y[-2] = 2 के लिए तंत्र की पद अनुक्रिया
(b) (i) चित्र 4(b) में प्रदर्शित तार्किक परिपथ का सत्यापन, तार्किक समीकरण ज्ञात करके तथा सत्यता तालिका निर्माण करके कीजिए।
(ii) एक 8 से 1 बहुलक (मल्टीप्लेक्सर) तथा तार्किक द्वारों का प्रयोग निम्नलिखित फलन का कार्यान्वयन करने के लिए कीजिए :
F(A, B, C, D, E) = Σ m (0, 1, 2, 4, 5, 6, 7, 13, 14, 20, 21, ..., 28, 29, 30, 31)
(c) चित्र 4(c) में प्रदर्शित प्रतिप प्रवर्धक (इनवर्टिंग एम्पलीफायर) की बंद पाश लब्धि का मान ज्ञात कीजिए । R₁ → 0 या R₃ → 0 की स्थिति में परिणाम की व्याख्या कीजिए ।
चित्र 4(c)
Answer approach & key points
(a) calculate: given > formula > substitution > result with units > interpretation | (b) describe: define > structure or process in order > labelled diagram > significance | (c) calculate: given > formula > substitution > result with units > interpretation Full marks: Complete derivations with correct logic and clear explanations of all limiting cases.
- Factor the denominator (poles ⅓ and ⅔) and expand H(z) in partial fractions to get h[n] = ½[(1/3)ⁿ⁻¹ + (2/3)ⁿ⁻¹]u[n − 1].
- Obtain the zero-state step response 9/4 − (3/4)(1/3)ⁿ − (3/2)(2/3)ⁿ.
- Include the initial-condition term via the one-sided transform to get y[n] = 9/4 − (23/36)(1/3)ⁿ − (19/18)(2/3)ⁿ.
- Derive Y as the sum of eight terms S₂^S₁^S₀^Dᵢ, showing that the circuit is an 8-to-1 MUX with the truth table 000 → D₀ … 111 → D₇.
- Take A, B, C as selects and find the data inputs I₀ = (DE)′, I₁ = 1, I₂ = 0, I₃ = D ⊕ E, I₄ = 0, I₅ = I₆ = I₇ = 1.
- Account for every minterm of the function and state the gates needed (one NAND and one XOR).
- Use the virtual ground at the inverting node to get V_x = −(R₃/R₂)V_in and apply KCL at V_x.
- Derive V_out/V_in = −(R₁ + R₃ + R₁R₃/R₄)/R₂.
- Explain that R₁ → 0 gives −R₃/R₂ and R₃ → 0 gives −R₁/R₂, with the T-network's multiplying action lost.