Q1 50M Compulsory solve Network analysis, signals, DC machines, transistors, digital logic
(a) In Figure 1(a) shown below, the two-port network is characterized in terms of y-parameters with y₁₁ = 3·3 × 10⁻³ S, y₂₂ = 5 × 10⁻³ S and y₁₂ = y₂₁ = 0. Find the voltage across 200 Ω load. (10 marks)
(b) For the signal shown in Figure 1(b), calculate the total energy of the signal X(t). Also sketch y(t) = X(10t – 5). (10 marks)
(c) A 220 V dc shunt motor has armature resistance Rₐ = 0·13 Ω, field resistance Rf = 250 Ω and rotational loss 230 W. On full-load, the line current is 9·5 A with the motor running at 1440 rpm. Determine the following:
(i) The mechanical power developed
(ii) The power output
(iii) The load torque
(iv) The full-load efficiency (10 marks)
(d) For the transistor circuit shown in Figure 1(d), determine the value of reverse saturation current, I_S, that would give a collector current of 1 mA, if β = 80, V_A = ∞ and V_T = 26 mV at T = 300 K. (10 marks)
(e) Consider the four variables logic function defined as follows:
F (A, B, C, D) = ĀC + ĀD + B̄C + B̄D + ABC̄ D̄
Assuming input variables as A, B, C and D, propose a logic circuit using only three logic gates to implement the function. (10 marks)
हिंदी में पढ़ें
(a) चित्र 1(a) में प्रदर्शित द्वि-प्रद्वार जालक्रम के, y-प्राचलों y₁₁ = 3·3 × 10⁻³ S, y₂₂ = 5 × 10⁻³ S तथा y₁₂ = y₂₁ = 0 के रूप में लक्षण बताए गए हैं । 200 Ω भार के आर-पार वोल्टता का मान ज्ञात कीजिए । (10 अंक)
(b) चित्र 1(b) में प्रदर्शित संकेत के लिए, संकेत X(t) की संपूर्ण ऊर्जा की गणना कीजिए । y(t) = X(10t – 5) का आरेखण भी कीजिए । (10 अंक)
(c) एक 220 V dc समानान्तर क्रम मोटर का, आर्मेचर प्रतिरोध Rₐ = 0·13 Ω, क्षेत्र प्रतिरोध Rf = 250 Ω तथा घूर्णन हान 230 W है । मोटर के 1440 rpm पर पूर्ण भार पर चलते समय लाइन धारा का मान 9·5 A है । निम्नलिखित का मान ज्ञात कीजिए :
(i) विकसित (उत्पन्न) यांत्रिक शक्ति
(ii) निर्गत शक्ति
(iii) भार (लोड) बल-आघूर्ण
(iv) पूर्ण भार दक्षता (10 अंक)
(d) चित्र 1(d) में प्रदर्शित ट्रांजिस्टर परिपथ के लिए, व्युत्क्रम संतृप्त धारा I_S का वह मान ज्ञात कीजिए जो संग्राहक धारा का मान 1 mA कर दे, यदि T = 300 K पर β = 80, V_A = ∞ तथा V_T = 26 mV हो । (10 अंक)
(e) निम्नानुसार परिभाषित चतुर्वर तार्किक फलन पर विचार कीजिए :
F (A, B, C, D) = ĀC + ĀD + B̄C + B̄D + ABC̄ D̄
A, B, C और D को निवेश चर मानकर केवल तीन तार्किक द्वारों का प्रयोग करते हुए इस फलन के कार्यान्वयन के लिए तार्किक परिपथ प्रस्तावित कीजिए । (10 अंक)
Answer approach & key points
Solve each sub-part systematically with clear step-by-step calculations. For part (a), apply y-parameter equations to find load voltage; for (b), compute energy using ∫|x(t)|²dt and apply time-scaling/shifting for the sketch; for (c), calculate motor performance parameters using DC machine equations; for (d), use Ebers-Moll model with given β; for (e), simplify the Boolean expression using K-map or algebraic manipulation to implement with only three gates. Allocate approximately 15% time to (a), 15% to (b), 25% to (c), 15% to (d), and 30% to (e) due to its simplification complexity.
- Part (a): Correct application of y-parameter equations I₁ = y₁₁V₁ + y₁₂V₂ and I₂ = y₂₁V₁ + y₂₂V₂ with y₁₂ = y₂₁ = 0, leading to V₂ = -I₂R_L and solving for load voltage
- Part (b): Energy calculation using E = ∫_{-∞}^{∞} |X(t)|² dt for the given waveform, correct application of time scaling (compression by 10) and time shifting (advance by 0.5s) for y(t) = X(10t-5)
- Part (c)(i)-(iv): Correct calculation of field current I_f = V/R_f, armature current I_a = I_L - I_f, back EMF E_b = V - I_aR_a, mechanical power P_mech = E_b × I_a, output power P_out = P_mech - rotational losses, torque T = P_out/ω, and efficiency η = P_out/(V×I_L)
- Part (d): Application of I_C = βI_B with I_B = I_S(e^{V_BE/V_T} - 1), using active mode assumption and given β = 80, V_T = 26mV to solve for I_S
- Part (e): Boolean simplification of F = ĀC + ĀD + B̄C + B̄D + ABC̄D̄ to minimal form using consensus theorem or K-map, resulting in implementation using only three logic gates (e.g., two AND-OR or NAND-NAND structure)
- Correct unit handling throughout (Siemens, Volts, Amperes, Watts, rad/s, Nm) and proper significant figures in final answers
Q2 50M solve Thevenin's theorem, convolution, sequential circuits
(a) Find the Thevenin's equivalent of the circuit shown in Figure 2(a) below as seen from the load impedance Z_L. Also find the value of Z_L for maximum power transfer. (20 marks)
(b) (i) Compute the convolution X[n] * h[n], where
X[n] = (1/2)^(-n) u[-n-2]
h[n] = u[n-2].
(ii) Consider the signal X(t) shown in Figure 2(b)(ii) below. Represent the signal X(t) in terms of rectangular pulse signal V(t) shown in the same figure. (20 marks)
(c) Consider the circuit shown in Figure 2(c) below. Let inputs A, B and C be all initially LOW. Output Y is supposed to go HIGH only when A, B and C go HIGH in a certain sequence. Determine the sequence that will make Y go HIGH. Modify this circuit to use D-Flip-flops. (10 marks)
हिंदी में पढ़ें
(a) चित्र 2(a) में प्रदर्शित परिपथ का, भार प्रतिबाधा Z_L से दृश्य थेवेनिन समतुल्य ज्ञात कीजिए। अधिकतम शक्ति अंतरण के लिए Z_L का मान भी ज्ञात कीजिए। (20 अंक)
(b) (i) संवलन (कनवोल्यूशन) X[n] * h[n] की गणना कीजिए, जहाँ
X[n] = (1/2)^(-n) u[-n - 2]
h[n] = u[n - 2].
(ii) चित्र 2(b)(ii) में प्रदर्शित संकेत X(t) पर विचार कीजिए । उसी चित्र में प्रदर्शित आयताकार स्पंद संकेत V(t) के सापेक्ष संकेत X(t) का निरूपण कीजिए । (20 अंक)
(c) चित्र 2(c) में प्रदर्शित परिपथ पर विचार कीजिए । माना कि प्रारंभ में निवेश A, B और C सभी निम्न (लो) हैं । A, B और C के किसी एक विशेष प्रक्रम में उच्च (हाई) होने पर निर्गत Y का उच्च होना अपेक्षित है । उस प्रक्रम को ज्ञात कीजिए जो Y को उच्च स्तर पर ले जाएगा । इस परिपथ को D-फ्लिप-फ्लॉपों का प्रयोग करने के लिए परिवर्तित कीजिए । (10 अंक)
Answer approach & key points
Solve this multi-part numerical problem by allocating approximately 40% time to part (a) Thevenin's equivalent and maximum power transfer, 40% to part (b) convolution and signal representation, and 20% to part (c) sequential circuit analysis and D-flip-flop modification. Begin each sub-part with the relevant circuit diagram or signal sketch, show all mathematical steps clearly, and conclude with the final numerical answer or circuit modification. For part (b)(i), carefully handle the time-reversed nature of x[n] and the shifted unit step functions.
- Part (a): Correct calculation of Thevenin's equivalent voltage (V_th) by open-circuit analysis and Thevenin's equivalent impedance (Z_th) by deactivating independent sources
- Part (a): Application of maximum power transfer theorem stating Z_L = Z_th* (complex conjugate) for AC circuits, or Z_L = Z_th for purely resistive circuits
- Part (b)(i): Proper handling of convolution with anti-causal signal x[n]=(1/2)^(-n)u[-n-2] rewritten as 2^n u[-n-2], correct determination of overlap regions for n<0 and n≥0
- Part (b)(ii): Expression of x(t) as weighted sum of shifted rectangular pulses V(t), identification of amplitude and time-shift parameters from figure
- Part (c): Analysis of sequential circuit to determine required input sequence (likely A→B→C or specific order) that activates Y through state transitions
- Part (c): Correct modification to D-flip-flops: converting existing flip-flops or designing equivalent state machine with proper excitation table and next-state logic
Q3 50M calculate Analog circuits and signal processing
(a) (i) Explain what happens when a circuit shown in Figure 3(a)(i) below is constructed using logarithmic amplifier. 10
Figure 3(a)(i)
(ii) Explain what happens if the topology is modified as shown in Figure 3(a)(ii) below. 10
Figure 3(a)(ii)
(b) For the circuit shown in Figure 3(b), calculate the voltage V₀(t) as function of time,
Figure 3(b)
where V(t) = 10 sin (6t + 60°) V and I(t) = 5 cos (4t + 30°) A. 20
(c) A mixer (analog multiplier) is used as a process in some analog communication systems. Two signals X₁(t) and X₂(t) are mixed to produce the output y(t) = X₁(t) X₂(t).
If X₁(t) = 10 sin c (10t) and X₂(t) = 2 cos (1000 πt), then calculate and plot the magnitude of the Fourier transform of output signal. Further, specify and prove the property of Fourier transform used in calculations. 10
हिंदी में पढ़ें
(a) (i) समझाइए कि जब चित्र 3(a)(i) में प्रदर्शित परिपथ को लघुगणकीय प्रवर्धक का प्रयोग करते हुए निर्मित किया जाएगा, तो क्या होगा ।
चित्र 3(a)(i)
(ii) समझाइए कि यदि संस्थितिकी को चित्र 3(a)(ii) में दर्शाए अनुसार परिवर्तित कर दिया जाए, तो क्या होगा ।
चित्र 3(a)(ii)
(b) चित्र 3(b) में प्रदर्शित परिपथ के लिए वोल्टता V₀(t) की गणना समय के फलन के रूप में कीजिए,
चित्र 3(b)
जहाँ V(t) = 10 sin (6t + 60°) V और I(t) = 5 cos (4t + 30°) A हैं।
(c) एक मिश्रक (अनुकृप गुणक) को किसी अनुकृप संचार प्रणाली के एक प्रक्रम के रूप में प्रयुक्त किया गया है । निर्गत y(t) = X₁(t) X₂(t) निर्मित करने के लिए दो संकेतों X₁(t) तथा X₂(t) को मिश्रित किया गया है ।
यदि X₁(t) = 10 sin c (10t) तथा X₂(t) = 2 cos (1000 πt) हो, तो निर्गत संकेत के फुरिये रूपांतर के परिमाण की गणना कीजिए तथा उसका आरेखण कीजिए । गणना में प्रयुक्त फुरिये रूपांतर के गुणों का उल्लेख कीजिए तथा उन्हें सिद्ध कीजिए ।
Answer approach & key points
The directive 'calculate' dominates part (b) carrying 20 marks, so allocate ~50% effort there with rigorous time-domain analysis; spend ~25% each on (a)(i) and (a)(ii) explaining logarithmic/antilogarithmic amplifier behavior with circuit diagrams; reserve ~10% for (c) applying the multiplication/convolution property of Fourier transforms. Structure: begin with conceptual explanations of log-amp configurations, proceed to detailed circuit analysis for V₀(t), and conclude with spectral analysis of the mixer output.
- For (a)(i): Explain that Figure 3(a)(i) realizes a log-amp producing V₀ = -V_T ln(V_i/R_1I_S), converting multiplication to addition for analog computation
- For (a)(ii): Explain the modified topology as an antilogarithmic (exponential) amplifier giving V₀ = -R_f I_S exp(-V_i/V_T), enabling division and power operations
- For (b): Apply KCL/KVL to derive the differential equation and solve for V₀(t) = 10 sin(6t + 60°) - L(di/dt) or equivalent, handling the frequency mismatch (6 rad/s vs 4 rad/s) correctly
- For (b): Show proper handling of phase relationships and superposition when input voltage and current have different frequencies
- For (c): Apply the multiplication property: F{x₁(t)x₂(t)} = (1/2π)[X₁(ω) * X₂(ω)], proving convolution in frequency domain shifts the sinc spectrum to ±1000π
- For (c): Sketch the resulting spectrum showing two sinc-shaped bands centered at ω = ±1000π with appropriate scaling and bandwidth 20π rad/s
Q4 50M calculate Digital signal processing and digital electronics
(a) Consider a discrete time system with transfer function given by
H(z) = Y(z)/R(z) = (z⁻¹ - ½z⁻²)/(1 - z⁻¹ + 2/9 z⁻²).
Calculate the following :
(i) The impulse response of the system
(ii) The step response of the system with zero initial conditions
(iii) The step response of the system with initial conditions y[-1] = 1 and y[-2] = 2 20
(b) (i) Verify by determining the logic equation for the output and by constructing the truth table for the logic circuit shown in Figure 4(b).
(ii) Use an 8 to 1 multiplexer and logic gates to implement the following function :
F(A, B, C, D, E) = Σ m (0, 1, 2, 4, 5, 6, 7, 13, 14, 20, 21, ..., 28, 29, 30, 31)
20
Figure 4(b)
(c) Determine the closed loop gain of the inverting amplifier shown in Figure 4(c) below. Explain the result if R₁ → 0 or R₃ → 0.
10
हिंदी में पढ़ें
(a) H(z) = Y(z)/R(z) = (z⁻¹ - ½z⁻²)/(1 - z⁻¹ + 2/9 z⁻²) द्वारा प्रदर्शित अंतरण फलन वाले एक असतत समय तंत्र पर विचार कीजिए तथा निम्नलिखित की गणना कीजिए :
(i) तंत्र की आवेग अनुक्रिया
(ii) शून्य प्रारंभिक स्थिति के लिए तंत्र की पद अनुक्रिया
(iii) प्रारंभिक स्थिति y[-1] = 1 तथा y[-2] = 2 के लिए तंत्र की पद अनुक्रिया
(b) (i) चित्र 4(b) में प्रदर्शित तार्किक परिपथ का सत्यापन, तार्किक समीकरण ज्ञात करके तथा सत्यता तालिका निर्माण करके कीजिए।
(ii) एक 8 से 1 बहुलक (मल्टीप्लेक्सर) तथा तार्किक द्वारों का प्रयोग निम्नलिखित फलन का कार्यान्वयन करने के लिए कीजिए :
F(A, B, C, D, E) = Σ m (0, 1, 2, 4, 5, 6, 7, 13, 14, 20, 21, ..., 28, 29, 30, 31)
(c) चित्र 4(c) में प्रदर्शित प्रतिप प्रवर्धक (इनवर्टिंग एम्पलीफायर) की बंद पाश लब्धि का मान ज्ञात कीजिए । R₁ → 0 या R₃ → 0 की स्थिति में परिणाम की व्याख्या कीजिए ।
चित्र 4(c)
Answer approach & key points
Calculate the required responses and circuit parameters systematically. For part (a) [20 marks], perform partial fraction expansion on H(z) and apply Z-transform properties for impulse and step responses, handling initial conditions via unilateral Z-transform. For part (b) [20 marks], derive the logic equation from Figure 4(b), construct truth table, then implement F(A,B,C,D,E) using 8:1 MUX with A,B,C as select lines. For part (c) [10 marks], apply ideal op-amp assumptions to find closed-loop gain and analyze limiting cases. Allocate approximately 40% time to (a), 35% to (b), and 25% to (c).
- Part (a)(i): Factor denominator, perform partial fraction expansion, identify poles at z=1/3 and z=2/3, obtain h[n] = [3(1/3)^n - 3(2/3)^n]u[n-1] or equivalent causal form
- Part (a)(ii): Apply step input R(z)=z/(z-1), use final value theorem or convolution sum, obtain y_step[n] with zero initial conditions
- Part (a)(iii): Apply unilateral Z-transform accounting for y[-1]=1, y[-2]=2, separate zero-state and zero-input responses, combine for total response
- Part (b)(i): Derive Boolean expression from Figure 4(b) circuit topology, verify with complete truth table showing all input combinations and output
- Part (b)(ii): Implement 5-variable function using 8:1 MUX with A,B,C as select inputs, determine D,E combinations for each minterm group (0-7, 13-14, 20-21, 28-31), connect appropriate logic to data inputs
- Part (c): Apply virtual ground concept, derive V_o/V_i = -R_f/R_1 where R_f involves R_2,R_3 network, analyze R_1→0 (infinite gain/saturation) and R_3→0 (gain becomes -R_2/R_1) cases with practical implications