(a) For the circuit shown in Figure 1(a), find the V_in, V_S and power supplied by the dependent source. (10 marks) (b) Calculate…

(a) V_in, V_S and Power of the Dependent Source Take the bottom wire as the 0 V reference and let the central top node be V. The 2 A (left branch) and 8 A (right branch) both flow into this node, while iₓ flows out down the middle branch, so KCL gives iₓ = 2 + 8 = 10 A. The dependent source fixes the right‑hand node at 4iₓ = 40 V; the 8 A flows left through the 2 Ω, so 40 − V = 8×2, giving V = 24 V. KVL around the left loop (V_in − 2×5 + 60 − V = 0) yields V_in = 24 + 10 − 60 = −26 V. For the middle branch, V = iₓ·3 + (−Vₛ) because the source's "−" terminal faces the 3 Ω, so 24 = 30 − Vₛ, giving Vₛ = 6 V (check: node below 3 Ω = −6 V, iₓ = (24−(−6))/3 = 10 A ✓). The dependent source has 40 V across it and the 8 A leaves its "+" terminal, so it supplies P = 40 × 8 = 320 W.

(b) Diode Forward Current The diode current is given by I = Iₛ[e^(V/nV_T) − 1] with ideality factor n = 1. First convert the temperature to Kelvin: T = 22 + 273 = 295 K. The thermal voltage is V_T = kT/q = (1.38×10⁻²³ × 295)/(1.6×10⁻¹⁹) = 4.071×10⁻²¹ / 1.6×10⁻¹⁹ = 0.02544 V (25.44 mV). The exponent is V/V_T = 0.8/0.02544 = 31.44, so e^31.44 ≈ 4.52×10¹³ (the "−1" is negligible at this magnitude). Substituting the reverse saturation current Iₛ = 12.674×10⁻¹³ A: I ≈ 12.674×10⁻¹³ × 4.52×10¹³ = ≈ 57.3 A. This large value illustrates the extreme sensitivity of the exponential term to the small thermal voltage: a modest 0.8 V forward bias produces a very large current, which is why real diodes are limited by series resistance and power rating rather than by the ideal equation at such voltages.

(c) Efficiency of the Long-Shunt Compound Generator At 75 % load the output power is P_out = 0.75 × 250 kW = 187.5 kW at V = 230 V, so the load current is I_L = 187500/230 = 815.2 A. In a long‑shunt compound machine the shunt field is connected directly across the terminals, so the shunt field current is constant at I_sh = 13 A, and the armature current is Iₐ = I_L + I_sh = 828.2 A. The copper losses are: armature Iₐ²Rₐ = 828.2²×0.009 = 6173 W; series field Iₐ²R_se = 828.2²×0.003 = 2058 W; shunt field V·I_sh = 230×13 = 2990 W; total copper loss = 11221 W. The rotational (iron plus mechanical) loss is taken from the no‑load motor test, where the armature current is 25 A at rated voltage: 230 × 25 = 5750 W (subtracting the no-load armature and series-field copper loss, 25² × 0.012 = 7.5 W, gives 5742.5 W, which does not change the result). Total loss = 11221 + 5750 = 16971 W. Efficiency = P_out/(P_out + total loss) = 187500/(187500 + 16971) = 91.7 %.

(d) Op-Amp Circuit For an ideal op‑amp the inverting input is a virtual ground (V₋ = 0) and no current enters the input. (i) I₁ = (1 − 0)/10 kΩ = 0.1 mA; since no current flows into the op‑amp, KCL at the inverting node gives I₂ = I₁ = 0.1 mA. The 10 kΩ feedback resistor then gives 0 − V_X = I₂·10 k = 1 V, so V_X = −1 V. The 100 Ω resistor to ground carries I₃ = (0 − V_X)/100 = 1/100 = 10 mA (upward, per the arrow). KCL at node V_X gives I_L = I₂ + I₃ = 0.1 + 10 = 10.1 mA, which is independent of R_L. (ii) The output voltage is V₀ = V_X − I_L·R_L = −1 − 10.1×10⁻³ R_L. Requiring V₀ ≥ −13 V gives 10.1×10⁻³ R_L ≤ 12, so R_L,max = 12/0.0101 ≈ 1188 Ω (≈1.19 kΩ). (iii) Over R_L = 100 Ω → 1 kΩ, I_L remains 10.1 mA (no change), while V₀ moves from −1 − 1.01 = −2.01 V to −1 − 10.1 = −11.1 V, a change of −9.09 V.

(e) Even Parity Generator and Checker A parity bit generator appends one extra bit P to a data word so that the transmitted word has a controlled parity; a parity bit checker at the receiver recomputes the parity of the received word and flags an error if it disagrees with the expected value. For even parity, the total number of 1s (data plus P) must be even, which is achieved by setting P equal to the X‑OR of all data bits: P = d₁ ⊕ d₂ ⊕ … ⊕ dₙ. The 2‑input X‑OR truth table is 00→0, 01→1, 10→1, 11→0. Generator circuit: cascade X‑OR gates, for example for four bits, (d₁⊕d₂)⊕(d₃⊕d₄) = P. Checker circuit: feed the received parity bit into the same chain, E = d₁⊕d₂⊕d₃⊕d₄⊕P; E = 0 confirms even parity (no single‑bit error), while E = 1 indicates an error. Thus a single X‑OR tree both generates the even parity bit and, with P included, checks it.