(a) (i) Differentiate between the functions of Decade counter and BCD counter with example. (10 marks)

(ii) Draw the diagram of cascading BCD adders to add two three-digit decimal numbers. Also explain the function of this adder with suitable exampl

Question

(a) (i) Differentiate between the functions of Decade counter and BCD counter with example. (10 marks)

(ii) Draw the diagram of cascading BCD adders to add two three-digit decimal numbers. Also explain the function of this adder with suitable example. (10 marks)

(b) (i) A DSB-SC signal is transmitted over a noisy channel, with the power spectral density of the noise being as shown in Figure 8(b)(i). The message bandwidth is 4 kHz and the carrier frequency is 200 kHz. Assuming that the average power of the modulated wave is 10 watts, find the output signal-to-noise ratio of the receiver. (10 marks)

Figure 8(b)(i)

(ii) Consider the system shown in Figure 8(b)(ii). The signal x(t) is defined by :
x(t) = A cos 2π f_c t

The low-pass filter has unity gain in the passband and bandwidth W, where f_c < W. The noise n(t) is white with two-sided power spectral density 1/2 N_0. Determine the signal-to-noise ratio of y(t). (10 marks)

Figure 8(b)(ii)

(c) A single phase transformer, 2400/240 V, 10 kVA, 50 Hz has core loss of 153 W and full load copper loss of 224 W. Find all day efficiency for the following loading cycle : 25% overload for 2 hours, full load for 6 hours, half load for 8 hours, quarter load for 4 hours and no load for 4 hours. All loads are at unity p.f. (10 marks)

UPSC Answer Check · Accepted Answer

Solve all four sub-parts systematically, allocating approximately 25% time to each part given equal 10-mark weighting. Begin with clear conceptual definitions for (a)(i), followed by diagram construction for (a)(ii). For (b), apply communication theory formulas with careful PSD integration. For (c), compute energy losses over the loading cycle methodically. Present derivations stepwise with units at each stage.
- Clear distinction: Decade counter counts 0-9 then resets (MOD-10), while BCD counter outputs valid 4-bit BCD codes (0000-1001) for each decimal digit; example showing 7490 vs 4518 IC applications
- Cascaded BCD adder diagram showing three 4-bit BCD adder blocks with carry propagation between stages; example computation like 456 + 789 = 1245 demonstrating decimal correction
- DSB-SC SNR calculation: noise power integration over 196-204 kHz band, output SNR = (Si/ni) × (2/1) for coherent detection, correct handling of triangular PSD shape
- Coherent detector analysis: pre-filter noise power = N₀W, post-filter signal power = A²/4, SNR₀ = A²/(2N₀W) with proper bandwidth considerations
- All-day efficiency: energy output = Σ(kVA×time×pf) × 2400/240, energy losses = 153W×24h + 224W×[(1.25)²×2 + 1²×6 + 0.5²×8 + 0.25²×4] hours, final percentage calculation
- Proper unit handling throughout (W, kWh, dB where applicable) and verification of numerical reasonableness

Dimension	Weight	Max marks	Excellent	Average	Poor
Concept correctness	20%	10	Precise distinction between decade and BCD counters with valid IC examples; correct DSB-SC demodulation theory with coherent detection; proper transformer loss segregation (constant core vs variable copper); accurate communication system block diagram interpretation	Basic definitions correct but conflates decade/BCD relationship; applies standard SNR formula without PSD adaptation; computes efficiency but confuses instantaneous vs energy-based calculation	Fundamental confusion between counter types; treats DSB-SC as standard AM for SNR; uses incorrect loss formulas or ignores time-weighting in efficiency
Numerical accuracy	20%	10	Exact arithmetic: DSB-SC SNR matches integrated noise power (triangular PSD area calculation); transformer energy losses computed to 3+ significant figures; final efficiency 95.2-96.5% range; no calculation errors propagating	Correct formulas but arithmetic slips in PSD integration or time-weighting; efficiency within ±2% of correct value; minor unit conversion errors	Order-of-magnitude errors in noise power; completely wrong efficiency (<80% or >99%); ignores 24-hour basis or miscalculates load factors
Diagram quality	20%	10	Clear cascaded BCD adder showing three 4-bit adders with decimal correction logic (0110 adder) and carry chain; labeled blocks for hundreds/tens/units; clean signal flow arrows; optional but clear DSB-SC receiver block diagram for (b)	Functional BCD adder diagram but missing carry details or decimal correction; messy layout but recognizable structure; no receiver diagram where helpful	Incorrect binary adder shown instead of BCD; no diagram for (a)(ii); illegible or missing interconnections; wrong IC pinouts
Step-by-step derivation	20%	10	Explicit steps: (a)(ii) shows binary addition → invalid BCD detection → +0110 correction → carry propagation; (b)(i) shows PSD integration limits → noise power expression → SNR formula substitution; (c) tabulates load cycle → computes output energy → loss energy → efficiency ratio	Some intermediate steps shown but skips key transitions; jumps to final formulas without setup; correct final answers with minimal working	Only final answers with no derivation; incorrect formulas used without justification; missing critical steps like decimal correction or coherent detection gain
Practical interpretation	20%	10	Contextualizes BCD adders for digital voltmeters/calculators; notes DSB-SC bandwidth efficiency vs AM; explains why all-day efficiency matters for Indian distribution transformers with variable loading; suggests design improvements (amorphous core, proper sizing)	Brief mention of applications without elaboration; standard textbook observations; no connection to real-world transformer loading patterns	No practical context; purely mathematical treatment; incorrect application claims (e.g., BCD for binary computers)

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