(a) A unity feedback system is shown in the figure below. Determine the range of α for which the system is stable and the…

(a) Range of α for stability and for 5% steady-state error

The open-loop transfer function is G(s) = (s + α)/[s³ + (1 + α)s² + (α − 1)s + (1 − α)] with unity feedback, so the characteristic equation is 1 + G(s) = 0:

s³ + (1 + α)s² + (α − 1)s + (1 − α) + s + α = s³ + (1 + α)s² + αs + 1 = 0.

Routh array:

s³: 1, α s²: 1 + α, 1 s¹: [(1 + α)α − 1]/(1 + α) = (α² + α − 1)/(1 + α) s⁰: 1

All first-column entries must be positive. From the s² row, α > −1. From the s¹ row, α² + α − 1 > 0, whose roots are α = (−1 ± √5)/2 = 0.618 and −1.618; with α > −1 this requires α > 0.618. The system is stable for α > 0.618.

For the steady-state error to a unit step, the position error constant is Kp = lim G(s) as s → 0 = α/(1 − α), and

ess = 1/(1 + Kp) = (1 − α)/(1 − α + α) = 1 − α.

The requirement |ess| < 0.05 gives 0.95 < α < 1.05. Both requirements are met simultaneously for 0.95 < α < 1.05. Within this band the value α = 1 is special: the open-loop denominator becomes s³ + 2s² = s²(s + 2), the system is type 2 and the step error is exactly zero, in agreement with ess = 1 − α = 0.

(b) The 8085 program and its execution time

LXI SP, 5000H (10 T) loads the stack pointer with 5000H so that the CALL can save its return address on the stack.

LXI D, 00F9H (10 T) loads the register pair DE with 00F9H = 249, the loop count.

CALL SUBROUTINE 1 (18 T) pushes the address of the HLT instruction on the stack and transfers control to the subroutine.

Inside SUBROUTINE 1: DCX D (6 T) decrements the pair DE by one; it does not affect any flag, which is why the next two instructions are needed. MOV A, D (4 T) copies the high byte into the accumulator, and ORA E (4 T) ORs it with the low byte: the result is zero, and the zero flag is set, only when both D and E are zero, i.e. when DE has counted down to 0000H. JNZ SUBROUTINE 1 (10 T when the jump is taken, 7 T when it is not) repeats the loop while DE is not zero. RET (10 T) pops the return address and returns to the main program, and HLT (5 T) stops the processor.

The segment is therefore a software delay loop of 249 passes. The loop body DCX D + MOV A, D + ORA E takes 14 T-states and is executed 249 times; JNZ is taken 248 times (10 T each) and falls through once (7 T):

loop = 249 × 14 + 248 × 10 + 7 = 3486 + 2480 + 7 = 5973 T-states.

Adding the two LXIs, CALL, RET and HLT, 10 + 10 + 18 + 10 + 5 = 53 T-states, the total is 6026 T-states. At 3 MHz one T-state is 0.333 μs, so the execution time is 6026 × 0.333 μs = 2.01 ms (2.007 ms up to the RET, if HLT is not counted). The program produces a delay of about 2 ms.

(c) Change in output voltage of the strain gauge

The strain produced by the stress is ε = σ/E = (120 × 10⁶)/(200 × 10⁹) = 6 × 10⁻⁴.

The change in gauge resistance is ΔR = Gf ε R = 2 × 6 × 10⁻⁴ × 100 = 0.12 Ω.

The gauge (100 Ω) and the load resistance (200 Ω) form a potential divider across 24 V. Taking the output across the gauge, before straining V₀ = 24 × 100/300 = 8.000 V, and after straining V₀' = 24 × 100.12/300.12 = 8.0064 V. The change is ΔV₀ = 6.4 mV.

The same figure follows from the small-change formula ΔV₀ ≈ V RL ΔR/(R + RL)² = 24 × 200 × 0.12/300² = 6.4 mV. The output voltage rises by 6.4 mV for the 120 MN/m² stress (if the output is taken across the load resistor it falls by the same amount).