(a) The figure below shows the encoder for a rate r = 1/2, constraint length k = 4 convolutional code : [Figure: input feeding…

(a) The rate-1/2, constraint-length-4 convolutional encoder

The encoder has three flip-flops in cascade. Let m₀ be the current message bit at the input, and m₁, m₂, m₃ the contents of the first, second and third flip-flop (the previous three bits). Reading the taps off the figure, the upper modulo-2 adder is fed from the input, from the first and second flip-flop outputs and from the third; the lower adder is fed from the input, from the first flip-flop output and from the third. The generator sequences are therefore

g⁽¹⁾ = (1, 1, 1, 1), g⁽¹⁾(x) = 1 + x + x² + x³, output c₁ = m₀ ⊕ m₁ ⊕ m₂ ⊕ m₃, g⁽²⁾ = (1, 1, 0, 1), g⁽²⁾(x) = 1 + x + x³, output c₂ = m₀ ⊕ m₁ ⊕ m₃.

The commutator sends c₁ then c₂ for every input bit, giving rate 1/2 with constraint length K = 4.

(i) Encoder output for 11011. Start with the register cleared, and follow the message with three zeros to flush it (the state after the fifth bit is shown so the tail can be checked). State = (m₁ m₂ m₃).

bit 1, state 000: c₁ = 1, c₂ = 1 → 11; next state 100 bit 1, state 100: c₁ = 1⊕1 = 0, c₂ = 1⊕1 = 0 → 00; next state 110 bit 0, state 110: c₁ = 0⊕1⊕1 = 0, c₂ = 0⊕1 = 1 → 01; next state 011 bit 1, state 011: c₁ = 1⊕0⊕1⊕1 = 1, c₂ = 1⊕0⊕1 = 0 → 10; next state 101 bit 1, state 101: c₁ = 1⊕1⊕0⊕1 = 1, c₂ = 1⊕1⊕1 = 1 → 11; next state 110 flush 0, state 110: → 01; next state 011 flush 0, state 011: → 01; next state 001 flush 0, state 001: → 11; next state 000

The encoded sequence is 11 00 01 10 11 for the five message bits, followed by 01 01 11 for the tail: 1100011011 010111.

The same result follows by polynomial multiplication. The message polynomial is m(x) = 1 + x + x³ + x⁴, and

c₁(x) = g⁽¹⁾(x) m(x) = (1 + x + x² + x³)(1 + x + x³ + x⁴) = 1 + x³ + x⁴ + x⁷ (all other terms cancel in pairs modulo 2), i.e. c₁ = 1 0 0 1 1 0 0 1; c₂(x) = g⁽²⁾(x) m(x) = (1 + x + x³)(1 + x + x³ + x⁴) = 1 + x² + x⁴ + x⁵ + x⁶ + x⁷, i.e. c₂ = 1 0 1 0 1 1 1 1.

Interleaving c₁ and c₂ gives 11 00 01 10 11 01 01 11, as before.

(ii) Code tree. The tree starts at the cleared state. From every node two branches leave: the upper branch for an input 0 and the lower branch for an input 1, each labelled with the two output bits (c₁c₂) that the input produces from that node's state. From the root, input 0 gives 00 and input 1 gives 11. From the node reached by 1 (state 100), input 0 gives 11 and input 1 gives 00. From state 110, input 0 gives 01 and input 1 gives 10; from state 010, 0 gives 10 and 1 gives 01; and so on for each of the eight states. Because the encoder has only 2³ = 8 states, from the fourth level on the tree repeats itself: the pattern of branch labels leaving any node depends only on the state, so the tree can be folded into the eight-state trellis.

Tracing the message 11011 through the tree: lower branch (11), lower branch (00), upper branch (01), lower branch (10), lower branch (11). The labels read off the path are 11 00 01 10 11, exactly the output found in (i); the tree is the encoder's state machine drawn out in time, so the two must agree.

(b)(i) Automatic load frequency control

The frequency of a power system is set by the balance between mechanical power input and electrical load: when load rises the generators slow down and frequency falls, and the reverse when load falls. Frequency must be held within tight limits (49.9–50.05 Hz under the Indian Grid Code) because turbine blades, motors, clocks and the whole synchronous operation of the grid depend on it; a sustained deviation trips under-frequency relays and can cascade into a blackout. Load changes continuously and unpredictably, and the primary governor action alone leaves a steady-state error proportional to the droop, so automatic load frequency control is needed to (1) restore frequency to nominal after every load change, (2) hold the scheduled tie-line interchange between control areas, and (3) share the load change among generators economically. The frequency and voltage loops are separate because real power affects frequency while reactive power affects voltage.

The schematic has two regulators on one machine. The load-frequency regulator: a speed sensor on the shaft compares the frequency with the reference, the error, together with the tie-line power error (weighted to form the area control error, ACE = ΔPtie + B Δf), is passed through an integrator and a speed changer that adjusts the governor set point; the governor operates the hydraulic amplifier and steam valve, and the turbine output follows. The automatic voltage regulator: a potential transformer at the terminals feeds a comparator with the voltage reference, the amplified error drives the exciter, which sets the field current and hence the terminal voltage. The two loops are drawn side by side on the generator, the AVR acting on the field and the ALFC on the prime mover.

(b)(ii) Sharing a 600 MW load between two generators

Droop is the fall in frequency from no load to full load as a fraction of rated frequency. Generator 1 (200 MW, 4%) drops 2 Hz over 200 MW, so its characteristic is P₁ = (200/2)(50 − f) = 100(50 − f) MW; generator 2 (400 MW, 6%) drops 3 Hz over 400 MW, so P₂ = (400/3)(50 − f) = 133.3(50 − f) MW. Both run at the common system frequency f, so

P₁ + P₂ = 233.3(50 − f) = 600 → 50 − f = 2.571 Hz, f = 47.43 Hz.

Then P₁ = 100 × 2.571 = 257.1 MW and P₂ = 133.3 × 2.571 = 342.9 MW.

The 600 MW load equals the combined rating, but under free governor action the machine with the smaller droop takes the larger share in proportion to its rating: generator 1 is overloaded by 57 MW (29%) while generator 2 is 57 MW under its rating, and the frequency has fallen to 47.43 Hz. For rating-proportional sharing the two droops would have to be equal, and the frequency would have to be restored by supplementary (secondary) control raising the set points.

(c) HVDC links

Monopolar link: a single conductor, usually at negative polarity to reduce corona and radio interference, with the return through the earth or sea; two converter stations, one at each end. Cheapest, used for cable crossings and as the first stage of a bipolar scheme; the disadvantages are the continuous ground current (corrosion of buried structures, interference with telecommunications) and no redundancy.

Bipolar link: two conductors, one positive and one negative with respect to earth, each with its own converter, the mid-points grounded at one or both ends. In normal operation the earth carries only the small unbalance current; if one pole fails the other continues at half power with ground return. This is the standard for long overhead lines (Rihand–Dadri ±500 kV, Talcher–Kolar ±500 kV, the ±800 kV Champa–Kurukshetra and Raigarh–Pugalur links). It costs more than monopolar but gives redundancy and low earth current.

Homopolar link: two or more conductors of the same polarity, usually negative, with ground return. It has the corona advantage of negative polarity and allows both conductors to be used when one converter is out, but the permanent ground current is its weakness and it is now rare.

Back-to-back link: both converters in the same station with no DC line, used to tie asynchronous systems or systems of different frequency (the Vindhyachal, Chandrapur, Sasaram and Gazuwaka stations that joined India's regional grids). Multi-terminal links connect three or more converter stations (the North-East–Agra ±800 kV scheme).

Advantages common to HVDC: no stability limit on line length, lower line cost and losses beyond the break-even distance (about 600–800 km overhead, 40–50 km cable), no charging current, control of power flow, asynchronous interconnection, no contribution to short-circuit level, and fewer conductors and narrower right of way. By converter technology, line-commutated (LCC, thyristor) links suit bulk long-distance transfer, while voltage-source (VSC, IGBT) links control active and reactive power independently, need no strong AC grid and suit offshore wind and city in-feeds (the Pugalur–Thrissur ±320 kV VSC link). Disadvantages: expensive converter stations, harmonic generation needing filters, large reactive-power demand at the converters (about 50–60% of the DC power), difficulty of breaking DC current and hence of tapping or building meshed networks, and the need for voltage transformation to be done on the AC side.