(a) (i) The figure below shows a schematic diagram of shunt ohmmeter. It consists of a battery in series with an adjustable…

(a)(i) Shunt ohmmeter: design equations

In the shunt ohmmeter the battery E, the adjustable resistance R₁ and the switch S are in series, and the basic PMMC meter (resistance Rm, full-scale current Im) is connected directly across the output terminals A–B, in parallel with the unknown Rx. The meter therefore shares the battery current I₁ with Rx.

With A–B open, all of I₁ flows through the meter. R₁ is adjusted for full-scale deflection:

Ifs = E/(R₁ + Rm), so R₁ = E/Ifs − Rm.

With Rx connected, the battery sees R₁ in series with Rm ∥ Rx, and the meter current is the current-divider share of I₁:

I₁ = E/[R₁ + Rm Rx/(Rm + Rx)], Im = I₁ Rx/(Rm + Rx) = E Rx/(R₁Rm + R₁Rx + RmRx).

The deflection as a fraction of full scale is Im/Ifs = Rx(R₁ + Rm)/(R₁Rm + R₁Rx + RmRx), and half-scale deflection occurs at Rh = R₁Rm/(R₁ + Rm), the parallel combination of the meter and the series resistance. These are the design equations; the scale is marked from them.

Observations: with A–B shorted, Rx = 0, the meter is short-circuited and reads zero, so the zero-ohm mark is at the left of the scale (no deflection). With A–B open, Rx = ∞, the meter carries the full battery current and reads full scale, so infinity is at the right of the scale. The scale therefore runs the opposite way to a series ohmmeter, and it is non-linear, crowded towards the high-resistance end. The switch S is essential because the battery would otherwise discharge continuously through R₁ and the meter even with nothing connected; it also allows the meter to be set to zero (open circuit gives full scale, so the zero adjustment is made with A–B open).

(a)(ii) Series resistance and the 100 Ω mark

E = 2 V, Ifs = 2 mA, Rm = 20 Ω.

R₁ = E/Ifs − Rm = 2/0.002 − 20 = 1000 − 20 = 980 Ω.

For Rx = 100 Ω:

Im = E Rx/(R₁Rm + R₁Rx + RmRx) = 2 × 100/(980 × 20 + 980 × 100 + 20 × 100) = 200/(19,600 + 98,000 + 2,000) = 200/119,600 = 1.672 mA.

Im/Ifs = 1.672/2 = 0.836, so 100 Ω is marked at 83.6% of full scale. As a check, the half-scale resistance is Rh = 980 × 20/1000 = 19.6 Ω, and 100 Ω, being much larger than Rh, lies well up the scale, as found.

(b) The state-space system

A = [0 16 0 0; −1 −8 0 0; 4 8 1 15; 0 0 3 −3], B = [0; 0; 1; 0].

A is block lower-triangular: the first two states (x₁, x₂) evolve on their own through A₁₁ = [0 16; −1 −8], while (x₃, x₄) are driven by A₂₂ = [1 15; 3 −3], by the coupling A₂₁ = [4 8; 0 0] from the first pair, and by the input through B₂ = [1; 0].

(i) Eigenvalues. det(λI − A) = det(λI − A₁₁) det(λI − A₂₂). For A₁₁: λ² + 8λ + 16 = (λ + 4)², roots −4, −4. For A₂₂: λ² + 2λ − 48 = 0, roots λ = (−2 ± 14)/2 = 6 and −8. The eigenvalues are −4, −4, 6, −8; the system is unstable because of the mode at +6.

(ii) Controllable and uncontrollable modes. The input enters only x₃, and nothing in (x₃, x₄) feeds back into (x₁, x₂), because A₁₂ = 0. The pair (x₁, x₂) is therefore unaffected by u: the modes −4, −4 are uncontrollable. For the (x₃, x₄) subsystem the controllability matrix is [B₂ A₂₂B₂] = [1 1; 0 3], of rank 2, so the modes 6 and −8 are controllable.

(iii) Infinitely many gains. With state feedback u = −Kx, K = [k₁ k₂ k₃ k₄], only the third row of A changes:

A − BK = [0 16 0 0; −1 −8 0 0; 4−k₁ 8−k₂ 1−k₃ 15−k₄; 0 0 3 −3].

The closed loop keeps the block lower-triangular form, so its eigenvalues are those of A₁₁, still −4, −4, together with those of A₂₂ − B₂K₂, K₂ = [k₃ k₄]:

det(λI − (A₂₂ − B₂K₂)) = λ² + (2 + k₃)λ + (3k₃ + 3k₄ − 48).

The uncontrollable modes stay at −4, −4 whatever K is; the required set −5, −3, −4, −4 is reachable precisely because its uncontrollable part is already at −4, −4. Matching λ² + (2 + k₃)λ + (3k₃ + 3k₄ − 48) to (λ + 5)(λ + 3) = λ² + 8λ + 15 gives k₃ = 6 and 18 + 3k₄ − 48 = 15, k₄ = 15. The gains k₁ and k₂ do not appear in the characteristic polynomial, so every K = [k₁ k₂ 6 15] places the poles at −5, −3, −4, −4: there are infinitely many.

(iv) The unique K̄. The coupling from the uncontrollable states into the controllable ones is the block A₂₁ − B₂K₁, whose first row is [4 − k₁, 8 − k₂] and second row [0 0]. Choosing k₁ = 4, k₂ = 8 makes it zero, so that initial conditions on (x₁, x₂) never reach (x₃, x₄). Hence

K̄ = [4 8 6 15],

and the closed-loop matrix becomes [0 16 0 0; −1 −8 0 0; 0 0 −5 0; 0 0 3 −3] in its third row, fully decoupled, with eigenvalues −4, −4, −5, −3 as required.

(c)(i) The memory address register

The MAR holds the 16-bit address of the memory location the processor is about to read or write. During a machine cycle the address is transferred from the program counter (for an opcode fetch), the stack pointer (for PUSH, POP, CALL, RET) or the HL pair (for MOV M and other memory-referencing instructions) into the MAR, whose outputs drive the address bus. In the 8085 the higher byte appears on A15–A8 for the whole machine cycle, while the lower byte appears on the multiplexed lines AD7–AD0 only in T1; the ALE pulse latches it into an external 8-bit latch (74LS373), which thus acts as the external half of the MAR and holds the low address steady while AD7–AD0 carry data in T2–T3. The address decoder then selects the chip, and RD or WR strobes the transfer. The MAR is what keeps the address stable, and the memory selected, for the whole of the read or write.

(c)(ii) Registers of the 8085

8-bit registers: the accumulator A; the six general-purpose registers B, C, D, E, H and L; the flag register F (S, Z, AC, P, CY); and, not accessible to the programmer, the instruction register and the temporary registers W and Z. 16-bit registers: the program counter PC and the stack pointer SP.

The general-purpose registers pair up as BC, DE and HL for 16-bit operations: LXI loads a pair, INX and DCX increment and decrement it, PUSH and POP transfer it to and from the stack, DAD adds BC, DE, HL or SP to HL, XCHG exchanges DE and HL, and LDAX and STAX use BC or DE as a memory pointer. HL is the memory pointer M for the whole MOV/ADD/ANA family, and A with F forms the pair PSW for PUSH PSW and POP PSW.