(a) (i) List various interrupts in microprocessor 8085 in order of decreasing priority. Specify which of these are edge-sensitive…

(a)(i) Interrupts of the 8085

In decreasing order of priority: TRAP (RST 4.5, vector 0024H), RST 7.5 (003CH), RST 6.5 (0034H), RST 5.5 (002CH) and INTR, the lowest, which is non-vectored and takes its address from the instruction supplied on the data bus in the interrupt-acknowledge cycle.

Sensitivity: RST 7.5 is edge-sensitive (positive-edge triggered); the edge sets an internal flip-flop, so the request is remembered even if the line goes low again, until it is serviced or cleared by SIM or RESET. RST 6.5, RST 5.5 and INTR are level-sensitive: the line must be held high until the processor samples it at the end of the current instruction. TRAP is both edge- and level-sensitive: it must make a low-to-high transition and remain high until it is acknowledged.

TRAP's noise immunity comes from this double requirement. A noise spike produces an edge but does not stay high, so it fails the level test; a slowly rising or persistent high without a fresh edge fails the edge test, which also prevents the same TRAP from being recognised twice. A purely edge-triggered line (RST 7.5) would latch a spike; a purely level-triggered line (RST 6.5, 5.5, INTR) would respond to any noise present at the sampling instant. TRAP, being non-maskable and reserved for power failure and similar emergencies, is given the most robust trigger.

(a)(ii) MVI A, 0BH followed by SIM

0BH = 0000 1011. The SIM instruction interprets the accumulator as: D7 SOD = 0, D6 SDE = 0, D5 unused, D4 R7.5 = 0, D3 MSE = 1, D2 M7.5 = 0, D1 M6.5 = 1, D0 M5.5 = 1.

Because MSE = 1 the mask bits take effect: RST 7.5 is unmasked (enabled), RST 6.5 is masked and RST 5.5 is masked. R7.5 = 0, so any pending RST 7.5 request in its flip-flop is not cleared. SDE = 0, so the serial output data latch SOD is left unchanged. The segment therefore enables only the RST 7.5 interrupt among the three maskable RST inputs; the interrupt system as a whole must still be turned on with EI for RST 7.5 to be serviced.

(b) Maxwell bridge

The arms are: R₁ = 1.6 kΩ; the unknown coil (Rs + jωLs) adjacent to it; R₃ = 400 Ω in parallel with C₃ = 0.2 μF; and R₄ = 500 Ω. The source is 5 V at 100 Hz and the detector is across the mid-points. At balance the ratio of the impedances in the two arms on each side of the detector is equal:

R₁/Z₃ = (Rs + jωLs)/R₄, with 1/Z₃ = 1/R₃ + jωC₃,

so Rs + jωLs = R₁R₄(1/R₃ + jωC₃). Equating real and imaginary parts gives the balance equations

Rs = R₁R₄/R₃ and Ls = R₁R₄C₃,

both independent of frequency, which is the advantage of this bridge.

Rs = 1600 × 500/400 = 2000 Ω; Ls = 1600 × 500 × 0.2 × 10⁻⁶ = 0.16 H.

Q of the coil at the test frequency: Q = ωLs/Rs = 2π × 100 × 0.16/2000 = 0.050. The same figure comes from Q = ωC₃R₃ = 2π × 100 × 0.2 × 10⁻⁶ × 400 = 0.050. This is a very low-Q coil (Q < 1), below the medium-Q range (about 1 to 10) for which the Maxwell inductance–capacitance bridge is best suited, and balance converges slowly (sliding balance); for high-Q coils the balancing resistance R₃ would have to be impractically large and Hay's bridge is used instead.

(c) Transfer function by Mason's gain formula

Number the nodes along the forward path: R, n₁ (after G₁), n₂ (after G₂), n₃ (after G₃), n₄ (after G₄), C. There is one forward path, P₁ = G₁G₂G₃G₄, and four loops, each with transmittance −1 on its return branch:

L₁ = −1 (the self-loop at n₁), L₂ = −G₄ (n₃ → n₄ → n₃), L₃ = −G₃G₄ (n₂ → n₃ → n₄ → n₂), L₄ = −G₂G₃G₄ (n₁ → n₂ → n₃ → n₄ → n₁).

Non-touching pairs: L₁ touches only n₁, so it does not touch L₂ (nodes n₃, n₄) or L₃ (n₂, n₃, n₄); it does touch L₄. L₂, L₃ and L₄ all share n₄. There are no non-touching triples.

Δ = 1 − (L₁ + L₂ + L₃ + L₄) + (L₁L₂ + L₁L₃) = 1 + 1 + G₄ + G₃G₄ + G₂G₃G₄ + G₄ + G₃G₄ = 2 + 2G₄ + 2G₃G₄ + G₂G₃G₄.

Every loop touches the forward path, so Δ₁ = 1. Hence

C(s)/R(s) = P₁Δ₁/Δ = G₁G₂G₃G₄/(2 + 2G₄ + 2G₃G₄ + G₂G₃G₄).