Electrical Engineering 2024 Paper I 50 marks Compulsory Solve

Q1

(a) Find the voltage on points A and B of the given circuit : (10 marks) (b) Determine the Z-transform of $x[n] = n\left(\frac{1}{2}\right)^{n+2} u[n+2]$. Specify the properties used. (10 marks) (c) In the circuit diagram given here, T₁ and T₂ are transistors with matched characteristics. The transistor parameters in active region are β = 200 and V_BE = 688 mV. Find V_CE of transistor T₂ : (10 marks) (d) A Binary Coded Decimal (BCD) code is to be transmitted to a remote receiver. Bits are arranged as A₃ A₂ A₁ A₀. Design a circuit at the receiving end which has an error detector to check the legal BCD code and produce a HIGH for any error condition. (10 marks) (e) In the circuit given here, D₁ is an ideal diode and key K₁ is ON for a long period of time. Now at time t₀, key K₁ is opened. Draw the voltage waveform on capacitor C₁ and find the final steady-state voltage on the capacitor : L=10 mH, 9 V, K₁ Open at t₀, R₁=0·9 Ω, D₁, C₁=100 μF (10 marks)

हिंदी में प्रश्न पढ़ें

(a) दिए गए परिपथ के बिन्दु A एवं B पर वोल्टता ज्ञात कीजिए : (10 अंक) (b) $x[n] = n\left(\frac{1}{2}\right)^{n+2} u[n+2]$ का Z-रूपान्तर ज्ञात कीजिए। प्रयुक्त अभिलक्षणों का उल्लेख कीजिए। (10 अंक) (c) यहाँ दिए गए परिपथ आरेख में $T_1$ तथा $T_2$ समान अभिलक्षणों वाले ट्रांजिस्टर हैं। सक्रिय क्षेत्र में ट्रांजिस्टरों के प्राचल $\beta = 200$ एवं $V_{BE} = 688$ mV हैं। ट्रांजिस्टर $T_2$ के $V_{CE}$ का मान ज्ञात कीजिए : (10 अंक) (d) एक बाइनरी कोडेड डेसीमल (BCD) कोड को एक दूरस्थ अभिग्राही तक प्रेषित करना है। बिटों को A₃ A₂ A₁ A₀ क्रम में व्यवस्थित किया गया है। अभिग्राही छोर पर एक ऐसा परिपथ परिकल्पित कीजिए, जिसमें वैध BCD कोड जाँचने और किसी त्रुटि की स्थिति में HIGH जनित करने हेतु त्रुटि संसूचक हो। (10 अंक) (e) यहाँ दिए गए परिपथ में D₁ एक आदर्श डायोड है और कुंजी K₁ दीर्घविधि से चालु (ऑन) है। अब समय t₀ पर कुंजी K₁ को खोल दिया जाता है। संधारित्र C₁ पर वोल्टता का तरंग रूप रेखांकित कीजिए और संधारित्र पर अंतिम स्थिर-अवस्था वोल्टता का मान ज्ञात कीजिए : L=10 mH, 9 V, K₁ t₀ पर खुला है, R₁=0·9 Ω, D₁, C₁=100 μF (10 अंक)

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Approach

Solve each sub-part systematically with equal time allocation (~20% per part) since all carry equal marks. Begin with circuit analysis for (a), apply Z-transform properties for (b), use transistor biasing equations for (c), implement combinational logic for (d), and analyze transient response for (e). Present derivations first, followed by numerical calculations and diagrams where required.

Key points expected

  • For (a): Apply KCL/KVL or nodal analysis to find voltages at points A and B; identify series-parallel combinations and current paths
  • For (b): Use time-shifting property and differentiation property of Z-transform; rewrite x[n] as (1/4)·(n+2-2)(1/2)^(n+2)u[n+2] or apply shift then differentiate
  • For (c): Analyze current mirror or differential pair configuration; use I_C = βI_B and V_CE = V_CC - I_C·R_C with matched transistor characteristics
  • For (d): Design 4-input combinational circuit using K-map; detect illegal BCD states (1010-1111) with output HIGH for error; implement using NAND/NOR gates
  • For (e): Determine initial capacitor voltage when K₁ is ON (diode conducts, inductor acts as short); analyze RLC transient when K₁ opens with diode reverse bias

Evaluation rubric

DimensionWeightMax marksExcellentAveragePoor
Concept correctness20%10Correctly identifies: (a) appropriate network analysis method; (b) proper sequence of Z-transform properties (time-shift then differentiation or vice versa); (c) current mirror operation and active region biasing; (d) BCD validity check as 4-variable logic function; (e) initial steady-state and second-order RLC behaviorIdentifies most concepts correctly but confuses property order in (b), misidentifies transistor configuration in (c), or uses incomplete K-map coverage in (d)Fundamental errors: uses Laplace instead of Z-transform, assumes cutoff/saturation for active region, designs parity check instead of BCD range detector, ignores inductor energy storage in (e)
Numerical accuracy20%10Precise calculations: (a) correct voltage values with proper sign; (b) final X(z) = (z/4)/(z-0.5)² with correct ROC |z|>0.5; (c) V_CE accurate to mV; (d) minimized gate count; (e) correct damping classification and final V_CMinor arithmetic errors in 1-2 parts, correct final form but wrong coefficient in (b), or approximate V_CE within 5%Major calculation errors: wrong transform pair, incorrect β usage, logic function with 4+ minterms wrong, or wrong time constant by factor of 10
Diagram quality20%10Clear labeled diagrams: (a) original circuit with current directions; (c) transistor circuit with currents marked; (d) logic diagram with gate symbols and connections; (e) voltage waveform showing exponential decay with proper time constantsDiagrams present but missing labels, or hand-drawn without proper symbols; waveform shape correct but unlabeled axesMissing critical diagrams, unrecognizable symbols, or no waveform sketch for (e) despite explicit requirement
Step-by-step derivation20%10Systematic derivations: (a) nodal equations shown; (b) property application explicit with formula statements; (c) current relationships derived from V_BE; (d) truth table → K-map → minimized expression → circuit; (e) characteristic equation and roots shownSome steps skipped or 'hence proved' without intermediate working; final answer correct but derivation unclearNo derivation shown, only final answers; or incorrect derivation with circular reasoning
Practical interpretation20%10Physical insight: (a) voltage divider loading effects; (b) ROC significance for stability; (c) temperature compensation via matched pair; (d) error detection in digital communication (relevant to ISRO/DRDO systems); (e) diode protection and energy dissipation in inductorBrief mention of practical relevance without elaboration; generic statements about circuit applicationsNo physical interpretation; purely mathematical treatment ignoring engineering significance of results

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