(a) Find the voltage on points A and B of the given circuit : (10 marks) (b) Determine the Z-transform of x[n] = n(1/2)ⁿ⁺²…

(a) Let the node at the output of the 2 A current source, where the 5 V source and the 2 Ω–3 Ω divider are connected, be C. Since an ideal 5 V source is connected between C and ground with its positive terminal at C, V_C = 5 V.

At node A, apply Kirchhoff’s current law. The 10 V source feeds A through 2 Ω, node A is loaded by 2 Ω to ground, and the current-source branch draws exactly 2 A away from A. The 1 Ω resistor in that branch does not affect this KCL because the ideal current source fixes the branch current at 2 A. Therefore, (10 − V_A)/2 = V_A/2 + 2 10 − V_A = V_A + 4 2V_A = 6 V_A = 3 V.

For node B, the 5 V source fixes node C at 5 V. The path from C to ground is 2 Ω in series with 3 Ω, with B between them. Thus a simple voltage divider gives V_B = 5 × 3/(2 + 3) = 5 × 3/5 = 3 V.

Final: V_A = 3 V, V_B = 3 V.

(b) Given x[n] = n(1/2)^(n+2) u[n+2]. Write it as x[n] = (1/4) n (1/2)^n u[n+2]. Let a = 1/2. First find the Z-transform of y[n] = a^n u[n+2]. By definition, Y(z) = Σ_n=−2^∞ a^n z^(−n) = a^(−2) z² + a^(−1) z + Σ_n=0^∞ (a z^(−1))^n. With a = 1/2, a^(−2) = 4, a^(−1) = 2, so Y(z) = 4z² + 2z + z/(z − 1/2), with ROC |z| > 1/2.

Now use the n-multiplication property, Z{n y[n]} = −z dY(z)/dz. Differentiate: dY/dz = 8z + 2 − (1/2)/(z − 1/2)².

Since x[n] = (1/4) n y[n], X(z) = (1/4)(−z) dY/dz = (1/4)(−z)[8z + 2 − (1/2)/(z − 1/2)²] = −2z² − z/2 + z/[8(z − 1/2)²].

The ROC is determined by the right-sided exponential term, ROC: |z| > 1/2, with z = ∞ excluded because of the positive powers z² and z. Final: X(z) = −2z² − z/2 + z/[8(z − 1/2)²], |z| > 1/2.

(c) T₁ and T₂ are matched, so their base currents are equal because both have the same V_BE and same emitter ground. Let I_B1 = I_B2 = I_B. Then I_C1 = I_C2 = βI_B = 200 I_B.

The 560 Ω resistor supplies the diode-connected node of T₁. Its current is I_R = (12 − V_BE)/560 = (12 − 0.688)/560 = 11.312/560 = 0.0202 A = 20.2 mA.

At the common base node, KCL gives I_R = I_C1 + I_B1 + I_B2 = 200 I_B + I_B + I_B = 202 I_B. Therefore, I_B = 20.2 mA / 202 = 0.1 mA.

Hence I_C2 = β I_B = 200 × 0.1 mA = 20 mA.

The collector voltage of T₂ is found from the 470 Ω resistor: V_C2 = 12 − I_C2 × 470 = 12 − 0.020 × 470 = 12 − 9.4 = 2.6 V.

Since emitter of T₂ is grounded, V_CE2 = V_C2 − V_E2 = 2.6 − 0 = 2.6 V. Also V_C2 = 2.6 V > V_BE = 0.688 V, so T₂ is in the active region, consistent with the assumption.

Final: V_CE of T₂ = 2.6 V.

(d) For a 4-bit BCD code A₃A₂A₁A₀, the legal codes are 0000 to 1001, i.e. decimal 0 to 9. The illegal codes are 1010 to 1111. Therefore the error output E must be HIGH for the minterms 10, 11, 12, 13, 14, 15.

Thus E = Σm(10, 11, 12, 13, 14, 15). The invalid codes are: 1010, 1011, 1100, 1101, 1110, 1111.

Minimization by grouping gives E = A₃A₂ + A₃A₁ = A₃(A₂ + A₁).

So A₀ is not used at all, because once A₃ = 1 and either A₂ = 1 or A₁ = 1, the code is already greater than 9.

Circuit design: connect A₂ and A₁ to a two-input OR gate. Let its output be O = A₂ + A₁. Then connect O and A₃ to a two-input AND gate. The AND gate output is E = A₃O = A₃(A₂ + A₁). This output is HIGH for every illegal BCD code and LOW for all legal BCD codes.

Final: E = A₃(A₂ + A₁). Use an OR gate on A₂ and A₁ followed by an AND gate with A₃.

(e) Let t₀ = 0 for convenience. Before opening K₁, the key has been ON for a long time. In DC steady state, the inductor L behaves as a short circuit. The intermediate node is therefore at 9 V, so the ideal diode D₁ charges C₁ to V_C(0−) = 9 V. The resistor branch current is i_R = 9/0.9 = 10 A. This current flows through the inductor just before opening, so i_L(0−) = 10 A.

At t = 0, K₁ opens. The 0.9 Ω branch is removed. Initially the inductor current cannot change instantly, so 10 A flows through D₁ into C₁. While D₁ conducts, the diode is ideal, hence V_M = V_C.

Apply KVL around the loop containing the 9 V source, L, D₁ and C₁: 9 − V_C = L di_L/dt. Also, i_L = C dV_C/dt. Therefore, LC d²V_C/dt² + V_C = 9.

Initial conditions: V_C(0) = 9 V, i_L(0) = 10 A, so dV_C/dt(0) = i_L(0)/C = 10/(100 × 10⁻⁶) = 100000 V/s.

The natural frequency is ω = 1/√(LC) = 1/√(10 × 10⁻³ × 100 × 10⁻⁶) = 1/√(10⁻⁶) = 1000 rad/s.

The solution is V_C(t) = 9 + A cos(1000t) + B sin(1000t). Using V_C(0) = 9 V gives A = 0. Using dV_C/dt(0) = 100000 V/s gives 1000B = 100000, so B = 100 V. Thus, while D₁ conducts, V_C(t) = 9 + 100 sin(1000t) V.

The diode current is i_L(t) = C dV_C/dt = 10 cos(1000t) A. D₁ stops conducting when i_L(t) becomes zero: cos(1000t) = 0 1000t = π/2 t = π/2000 s ≈ 1.57 ms.

At that instant, V_C = 9 + 100 sin(π/2) = 9 + 100 = 109 V. After this, D₁ is reverse-biased and blocks any reverse current. The capacitor has no discharge path, so it retains its charge.

Waveform: before t₀, V_C is steady at 9 V. At t₀, V_C rises as a quarter-sine from 9 V to 109 V over π/2000 s. After that, it remains flat at 109 V.

Final steady-state voltage on C₁ = 109 V.