(a) Draw the circuit diagram, function table, logic symbol and switch model for a CMOS gate (using six transistors) with two inputs A and B and an output Z, such that Z = 0 if A = 1 and B = 0, and Z = 1 otherwise (20 marks)
(b) For the signals f₁(t)

Question

(a) Draw the circuit diagram, function table, logic symbol and switch model for a CMOS gate (using six transistors) with two inputs A and B and an output Z, such that Z = 0 if A = 1 and B = 0, and Z = 1 otherwise (20 marks)
(b) For the signals f₁(t) and f₂(t) shown in the figures below, find and sketch $\int_{-\infty}^{t} f(x)\,dx$ : (20 marks)
(c) In the circuit given here, find the value of voltage $v_1$ : (10 marks)

UPSC Answer Check · Accepted Answer

Begin with the directive 'draw' for part (a), which demands precise circuit diagrams, truth tables, and switch models for the 6-transistor CMOS gate implementing Z = NOT(A AND NOT(B)). Allocate approximately 40% of effort to part (a) given its 20 marks, 35% to part (b) for signal integration with proper sketching of ramp/step waveforms, and 25% to part (c) for the circuit analysis. Structure as: (a) complete CMOS characterization with all four required elements, (b) mathematical integration with graphical interpretation showing accumulation of area under curves, (c) systematic nodal/mesh analysis for v₁.
- Part (a): Correct identification of the logic function as Z = A' + B (OR gate with inverted A, or equivalently Z = NOT(A AND NOT(B))) with proper PMOS-NMOS network topology using exactly 6 transistors
- Part (a): Complete function table showing all four input combinations with correct output states, and accurate IEEE/ANSI logic symbol representation
- Part (a): Switch model clearly distinguishing conducting/non-conducting states for both pull-up (PMOS) and pull-down (NMOS) networks
- Part (b): Correct mathematical integration of f₁(t) and f₂(t) showing piecewise linear/quadratic results with proper handling of limits from -∞ to t
- Part (b): Accurate sketch of integrated signals showing ramp characteristics, continuity at transition points, and proper asymptotic behavior
- Part (c): Application of KCL/KVL or nodal analysis to solve for v₁, with identification of circuit topology (likely resistive divider, op-amp, or transistor circuit)
- Part (c): Correct numerical value with proper units and sign convention for v₁

Dimension	Weight	Max marks	Excellent	Average	Poor
Concept correctness	25%	12.5	For (a): correctly identifies the logic as Z = A' + B with proper CMOS complementary network design; for (b): applies fundamental theorem of calculus correctly with proper handling of piecewise integration limits; for (c): selects appropriate analysis method (nodal/mesh) with correct circuit laws application	Identifies basic logic function but makes minor errors in transistor sizing or network topology; integration concept understood but limits handled incorrectly; applies KCL/KVL with minor sign errors	Fundamental misunderstanding of CMOS operation (e.g., PMOS in pull-down), incorrect logic function identification, or failure to recognize integration as area accumulation; major errors in circuit law application
Numerical accuracy	20%	10	Part (b): exact values of integrated functions at all critical time points with correct slopes and intercepts; part (c): precise value of v₁ with correct significant figures and unit handling (V, mV, etc.)	Correct approach but arithmetic errors in final values; integration constants determined incorrectly; v₁ calculation has minor computational slip	Major calculation errors, incorrect integration constants, wrong final answer by factor of 10 or more, or missing units throughout
Diagram quality	25%	12.5	Part (a): neat, labeled CMOS schematic with clear VDD, GND, input/output nodes, proper transistor symbols (gate, source, drain); standard logic symbol; clear switch model with ON/OFF states; part (b): properly scaled sketches with labeled axes, time markers, and asymptotic values	Diagrams present but labels incomplete, symbols non-standard, or sketches roughly drawn without proper scaling; missing some node labels or voltage levels	Unrecognizable schematics, missing essential components, no labels, or failure to provide required diagrams (circuit, symbol, switch model, or sketches)
Step-by-step derivation	20%	10	Clear progression from given information to solution: for (a) systematic derivation of transistor network from truth table; for (b) explicit integration steps with interval-wise breakdown; for (c) complete nodal equations with substitution steps shown	Steps present but logical jumps exist; some intermediate steps omitted; integration performed without showing interval transitions; circuit analysis skips equation setup	No visible derivation, only final answers; or completely wrong approach with incoherent steps; missing essential intermediate results
Practical interpretation	10%	5	For (a): comments on power dissipation, noise margins, or propagation delay relevance to Indian semiconductor industry (e.g., SCL Chandigarh); for (b): physical interpretation of integration as accumulator/integrator circuit behavior; for (c): practical significance of v₁ in circuit operation	Brief mention of practical relevance without elaboration; generic statements about CMOS advantages or integration applications	No practical context provided; purely mathematical/circuit treatment without connection to real-world EE applications or Indian industry context

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