(a) Draw the circuit diagram, function table, logic symbol and switch model for a CMOS gate (using six transistors) with two…

(a) The required function is Z = 0 only for A = 1, B = 0. Hence Z = ¬A + B = A → B.

Six-transistor CMOS realisation: use a 2-transistor inverter to generate B′; then a 4-transistor static CMOS gate.

Circuit diagram (six transistors; the inverter P3-N3 generates B′):

Pull-up network: P1 and P2 in parallel. Pull-down network: N1 and N2 in series.

Function table:

• A = 0, B = 0 → Z = 1
• A = 0, B = 1 → Z = 1
• A = 1, B = 0 → Z = 0
• A = 1, B = 1 → Z = 1

(Z is LOW only for A = 1, B = 0.)

Logic symbol: an OR gate with a bubble on the A input, B connected directly; output Z = ¬A + B.

Switch model:

The inverter switch model gives B′ = 0 when B = 1 and B′ = 1 when B = 0.

Check: for A = 1, B = 0, B′ = 1, so N1 and N2 both ON, P1 and P2 both OFF, Z = 0. For all other input combinations, the pull-up path is ON or the pull-down path is OFF, so Z = 1.

(b)(i) From the plot, f₁(t) = 0 for t < 0; f₁(t) = 1 for 0 ≤ t < 1; f₁(t) = −1 for 1 ≤ t < 3; f₁(t) = 0 for t > 3, with an impulse +1δ(t − 3) at t = 3.

Let y₁(t) = ∫ from −∞ to t f₁(x) dx.

For t < 0: y₁(t) = 0.

For 0 ≤ t < 1: y₁(t) = ∫ from 0 to t 1 dx = t.

For 1 ≤ t < 3: y₁(t) = ∫ from 0 to 1 1 dx + ∫ from 1 to t (−1) dx = 1 − (t − 1) = 2 − t.

For t ≥ 3: y₁(t) = 1 + (−2) + 1 = 0. Thus y₁(3) = 0; just before t = 3, y₁ → −1, so there is a jump of +1 at t = 3.

Sketch: y₁ rises linearly from 0 to 1 for 0 ≤ t ≤ 1; falls linearly from 1 to −1 for 1 ≤ t < 3; jumps to 0 at t = 3; stays 0 afterwards.

(b)(ii) From the plot, f₂(t) = 0 for t < 0; f₂(t) = 1 for t ≥ 0, with impulses −δ(t − 1), −δ(t − 2), −δ(t − 3).

Let y₂(t) = ∫ from −∞ to t f₂(x) dx.

For t < 0: y₂(t) = 0.

For 0 ≤ t < 1: y₂(t) = ∫ from 0 to t 1 dx = t.

For 1 ≤ t < 2: y₂(t) = ∫ from 0 to t 1 dx − 1 = t − 1.

For 2 ≤ t < 3: y₂(t) = ∫ from 0 to t 1 dx − 1 − 1 = t − 2.

For t ≥ 3: y₂(t) = ∫ from 0 to t 1 dx − 1 − 1 − 1 = t − 3.

At t = 1, 2, 3 the impulses cause downward jumps of 1. Sketch: y₂ rises linearly with slope 1 from 0 to 1 in each unit interval, then drops instantaneously to 0 at t = 1, 2, 3; after t = 3 it continues as t − 3.

(c) Use nodal analysis. Let the bottom rail be 0 V. In the right subcircuit, the 5 V source fixes node B at v_B = 5 V. Also v_A = v_x.

KCL at node A, taking currents leaving as positive: v_x/1 kΩ + 5 mA + (v_x − v_B)/4 kΩ = 0. Using kΩ and mA: v_x + 5 + (v_x − 5)/4 = 0. Multiply by 4: 4v_x + 20 + v_x − 5 = 0 5v_x + 15 = 0 v_x = −3 V.

Now KCL at the top node of the left circuit. Its voltage is v_1. The VCCS supplies v_x/20 mA upward. Thus: 12 mA + v_x/20 = v_1/2 kΩ + 2 mA. Using v_x = −3 V: 12 − 3/20 = v_1/2 + 2 12 − 0.15 − 2 = v_1/2 9.85 = v_1/2 v_1 = 19.7 V = 197/10 V.

Here all quantities are in the consistent set V, mA and kΩ, so the dependent source gives v_x/20 mA (a transconductance of 1/20 mS). If its gain were instead read as 1/20 A/V, it would deliver −150 mA and v₁ would be 2(12 − 150 − 2) = −280 V.

Final answer for (c): v₁ = 19.7 V.