(a) In the circuit diagram given here, load resistance R_L is to be set for maximum power transfer. Draw Thevenin equivalent…

(a) Thevenin equivalent at ab, R_L for maximum power, and loss in R₃

Circuit and references. Take the bottom wire (b) as reference. Let V_ab = V at node a, and let x be the node joining R₁, R₂ and the dependent source. The dependent source has its − terminal at x and its + terminal at a, so

V_a − V_x = 2V_ab ⇒ V_x = V − 2V = −V

R₃ (4 Ω) lies inside the network, across ab. R_L is the load.

Open-circuit voltage (R_L removed). The dependent voltage source links x and a, so treat them as a supernode. KCL (currents leaving): (V_x − 9)/12 + (V_x − 3)/12 + V/4 = 0 (−V − 9)/12 + (−V − 3)/12 + 3V/12 = 0 ⇒ (V − 12)/12 = 0 ⇒ V_th = V_oc = 12 V

Short-circuit current. With a–b shorted, V_ab = 0, so the dependent source is zero and V_x = 0. R₃ is also shorted. I_sc = (9 − 0)/12 + (3 − 0)/12 = 0.75 + 0.25 = 1 A

Thevenin resistance. R_th = V_oc/I_sc = 12/1 = 12 Ω. Check with the independent sources killed and a test voltage V at a: V_x = −V, so the current drawn from a is V/4 + (−V/12 − V/12) = V/12, giving R_th = 12 Ω again.

Maximum power transfer. R_L = R_th = 12 Ω. Then V_ab = 12/2 = 6 V and P_L,max = V_th²/(4R_th) = 144/48 = 3 W. A sweep of R_L (6, 10, 14, 20 Ω gives 2.67, 2.98, 2.98, 2.81 W) confirms the peak at 12 Ω.

Loss in R₃. R₃ carries the terminal voltage V_ab = 6 V: P_R₃ = 6²/4 = 9 W

Power balance with R_L = 12 Ω: V_x = −6 V; the 9 V source supplies 1.25 A (11.25 W) and the 3 V source 0.75 A (2.25 W). The dependent source carries 2 A with a 12 V rise (24 W). Total supplied = 37.5 W = R₁ (18.75) + R₂ (6.75) + R₃ (9) + R_L (3). The Thevenin model reproduces the load behaviour, but the internal loss (here in R₃) cannot be found from the equivalent. It must be computed in the original circuit.

(b)(i) Input bias current, input offset voltage, and a bias-compensated inverting amplifier

Input bias current (I_B) is the average of the dc currents flowing into the two input terminals of an op-amp when its output is at zero volts: I_B = (I_B₊ + I_B₋)/2. These currents are the base (or gate) currents of the input-stage transistors. Typical values are about 80 nA for a 741 and picoamperes for FET-input devices.

Input offset voltage (V_io) is the dc differential voltage that must be applied between the two input terminals to make the output exactly zero. It arises from mismatch in the input differential pair (typically about 1 mV, maximum 6 mV, for a 741). The related input offset current, I_io = |I_B₊ − I_B₋|, is the difference between the two bias currents (about 20 nA for a 741).

Circuit (gain −4). With R₁ = 10 kΩ and R_f = 40 kΩ, A_v = −R_f/R₁ = −4. To cancel the effect of the bias currents, connect the non-inverting input to ground through R_comp = R₁ ∥ R_f = (10 × 40)/50 = 8 kΩ, not directly.

Why it works. With vᵢ = 0, I_B₋ flowing through R₁ ∥ R_f produces an output error of about I_B₋R_f. The current I_B₊ through R_comp develops −I_B₊(R₁ ∥ R_f) at the + input, and that is amplified by (1 + R_f/R₁). The net output error is V₀ = R_f(I_B₋ − I_B₊) = R_f·I_io. The error now depends only on the much smaller offset current, not on the bias current.

(b)(ii) Series regulator: output range and worst-case dissipation in T₁

Operation. The 12 V Zener (fed from the input through 1 kΩ) is the reference. The divider 1 kΩ + 10 kΩ pot + 1 kΩ = 12 kΩ sits across it and feeds the pot wiper to the op-amp's + input. The − input is taken from the output terminal, so the op-amp and the pass transistor T₁ act as a voltage follower: V₀ = V_wiper. T₂, with its base-emitter across the 0.7 Ω sensing resistor, is the current limiter.

Adjustment range.

• Wiper at bottom: V₀,min = 12 × 1/12 = 1 V
• Wiper at top: V₀,max = 12 × 11/12 = 11 V

So the output can be set anywhere from 1 V to 11 V. The input (15 V minimum) always leaves enough headroom for T₁ at 11 V.

Current limit. T₂ turns on and diverts T₁'s base drive when I₀ × 0.7 Ω = V_BE ≈ 0.7 V, so I₀,max ≈ 1 A.

Worst-case dissipation in T₁. Dissipation P = V_CE × I is greatest at maximum input, maximum (limited) current and minimum output voltage:

• At V₀ = 1 V (lowest setting), V_in = 20 V, I = 1 A: V_CE = 20 − 1 − 0.7 = 18.3 V, so P = 18.3 W.
• Under an output short circuit (V₀ = 0), V_in = 20 V, I = 1 A: V_CE = 20 − 0.7 = 19.3 V, so P = 19.3 W. This is the absolute worst case.

T₁ and its heat sink must therefore be rated for about 20 W.

(c) Function of the three-multiplexer circuit

From the figure, the first-level multiplexers (I₀/I₁ and I₂/I₃) share select line S₁, and the output multiplexer (Z₁/Z₂) is selected by S₀. I assume the lower input of each MUX is chosen when its select is 0, which is consistent with I₀ being the lowest-numbered input.

Z₁ = S̄₁I₀ + S₁I₁ Z₂ = S̄₁I₂ + S₁I₃ Z = S̄₀Z₁ + S₀Z₂ = S̄₀S̄₁I₀ + S̄₀S₁I₁ + S₀S̄₁I₂ + S₀S₁I₃

• S₀ = 0, S₁ = 0: Z₁ = I₀, Z₂ = I₂, Z = I₀
• S₀ = 0, S₁ = 1: Z₁ = I₁, Z₂ = I₃, Z = I₁
• S₀ = 1, S₁ = 0: Z₁ = I₀, Z₂ = I₂, Z = I₂
• S₀ = 1, S₁ = 1: Z₁ = I₁, Z₂ = I₃, Z = I₃

Function: the circuit is a 4-to-1 multiplexer. Exactly one of I₀–I₃ reaches Z, and the selected input number is 2S₀ + S₁. Because of the wiring, S₀ acts as the most significant select bit and S₁ as the least significant. This shows how larger multiplexers are built as a tree of 2-to-1 units.