Paper I — Q4
(a) In the circuit diagram given here, load resistance R_L is to be set for maximum power transfer. Draw Thevenin equivalent…
In the circuit diagram given here, load resistance R_L is to be set for maximum power transfer. Draw Thevenin equivalent circuit across ab and calculate the value of R_L for maximum power transfer. Also calculate the power loss in resistance R_3, when the circuit is delivering maximum power to load R_L :
Define input bias current and input offset voltage for an OPAMP. Using an OPAMP, draw an inverting amplifier circuit with gain = –4 in such a way that the effect of bias current is minimized. 10 marks
In the linear regulated power supply circuit shown here, calculate the output voltage adjustment range and maximum power dissipation in transistor T₁ in worst case :
(T₁ and T₂ are Si transistors) 10 marks
A circuit using three 2-input multiplexers is shown below. Determine the function performed by this circuit :
हिंदी में प्रश्न पढ़ें
यहाँ दिए गए परिपथ आरेख में भार प्रतिरोध R_L को अधिकतम शक्ति अंतरण के लिए निर्धारित करना है। ab के आर-पार थेवेनिन समतुल्य परिपथ अंकित कीजिए और अधिकतम शक्ति अंतरण के लिए R_L के मान की गणना कीजिए। प्रतिरोध R_3 में शक्ति ह्रास की भी गणना कीजिए जब परिपथ, भार प्रतिरोध R_L को अधिकतम शक्ति प्रदान कर रहा हो :
एक OPAMP के लिए निवेश बायस धारा और निवेश ऑफसेट वोल्टता को परिभाषित कीजिए। एक OPAMP का प्रयोग करते हुए एक प्रतिलोम प्रवर्धक परिपथ आरेखित कीजिए जिसकी लब्धि = –4 ऐसे हो कि बायस धारा का प्रभाव न्यूनतम हो।
यहाँ प्रदर्शित रैखिक नियंत्रित शक्ति प्रदाय परिपथ में निर्गत वोल्टता समायोजन परास और सबसे खराब स्थिति में ट्रांजिस्टर T₁ में अधिकतम शक्ति क्षय की गणना कीजिए :
(टी₁ और टी₂, Si ट्रांजिस्टर हैं)
2 निवेशों वाले तीन मल्टीप्लेक्सरों का उपयोग करते हुए बनाया गया एक परिपथ नीचे प्रदर्शित है। इस परिपथ द्वारा निष्पादित कार्य ज्ञात कीजिए :
The figure this question refers to, in words
The question paper is a scan and the diagram did not survive as text. This is the figure as read from the original page — every component, value and label — so the question can be worked from the text below.
(a) A DC circuit diagram. On the left, a 9V DC voltage source (positive terminal up) is connected in series with a resistor R1 (12 Ohm). The right side of R1 connects to a node. From this node, a resistor R2 (12 Ohm) connects downwards to a 3V DC voltage source (positive terminal up), which connects to the bottom reference line. Also from the node after R1, a dependent voltage source is connected in series to the right. This source is a diamond shape labeled '2Vab' with the negative terminal on the left and positive on the right. The positive terminal of the dependent source connects to a top horizontal wire. This top wire connects to the top of a resistor R3 (4 Ohm) and to a terminal labeled 'a'. The bottom of R3 connects to a bottom horizontal wire, which also connects to the negative terminal of the 3V source and the negative terminal of the 9V source. The bottom wire connects to a terminal labeled 'b'. The voltage across terminals a and b is labeled 'Vab' with the positive reference at 'a'. A variable load resistor RL is connected in parallel with R3, between terminals a and b.
(b) A linear regulated power supply circuit. The input is a DC voltage source labeled 'Input 15 V to 20 V DC'. The positive input terminal connects to the top of a vertical resistor network and to the collector of a PNP transistor T1. The resistor network consists of a 1 kΩ resistor in series with a 10 kΩ potentiometer, followed by a 1 kΩ resistor to ground. The wiper of the 10 kΩ potentiometer connects to the non-inverting (+) input of an operational amplifier (OPAMP). The inverting (-) input of the OPAMP connects to the emitter of an NPN transistor T2. The OPAMP output connects to the base of T2 through a 470 Ω resistor. The emitter of T2 connects to the base of T1. The emitter of T1 connects to the output terminal and to the junction between the 10 kΩ potentiometer and the bottom 1 kΩ resistor. A 0.7 Ω resistor is connected between the emitter of T1 and the output terminal. The negative input terminal is connected to ground. T1 and T2 are specified as Si transistors.
(c) A logic circuit diagram enclosed in a dashed rectangular box. The circuit consists of three 2-to-1 multiplexers (labeled 'MUX'). The inputs are labeled I0, I1, I2, I3 and the output is labeled Z. The select lines are labeled S0 and S1. The first MUX (bottom left) has inputs I0 and I1 and select line S0; its output is labeled Z1. The second MUX (top left) has inputs I2 and I3 and select line S0; its output is labeled Z2. The third MUX (right) has inputs Z1 and Z2 and select line S1; its output is Z. The select line S1 is connected to the select input of the third MUX. The select line S0 is connected to the select inputs of the first two MUXes.
What "Calculate" is asking you to do
Apply the standard formula or schedule to data the question has already supplied — a table of readings, cost records, a balance sheet — and produce the number. The method is rarely in doubt; the marks sit in the named intermediate quantities, each of which has to appear as a labelled line.
Structure that answers it
Data as given → formula or standard treatment, named → substitution → each intermediate, labelled → result with units
Where marks are lost
Omitting an intermediate the marking scheme pays for separately, or rounding at an intermediate line so the final figure drifts. In commerce and accountancy, any figure in a statement that no numbered working note supports is treated as unearned.
How this answer will be evaluated
Approach
(a) calculate: given > formula > substitution > result with units > interpretation | (b(i)) define: precise definition > the distinguishing feature > one example | (b(ii)) calculate: given > formula > substitution > result with units > interpretation | (c) describe: define > structure or process in order > labelled diagram > significance Full marks: Complete circuit analysis with all required calculations, correct Thevenin equivalent, proper op-amp definitions with compensation, accurate power supply calculations, and clear MUX function identification with full working.
Key points expected
- Redraw circuit with polarities and reference directions marked
- Calculate Thevenin voltage V_th across terminals ab
- Calculate Thevenin resistance R_th across terminals ab
- Calculate power loss in R_3 at maximum power transfer
- Precise definition of input bias current
- Precise definition of input offset voltage
- Inverting amplifier circuit with gain = -4
- Compensation resistor to minimize bias current effect
Evaluation rubric
Each sub-part is marked on its own, against the marks and word limit printed on the paper.
- (a) Thevenin equivalent across ab, R_L for max power, and power loss in R_3. 20 marks
calculate— given → formula → substitution → result with units → interpretation
Must cover
- Redraw circuit with polarities and reference directions marked
- Calculate Thevenin voltage V_th across terminals ab
- Calculate Thevenin resistance R_th across terminals ab
- Calculate power loss in R_3 at maximum power transfer
Loses marks
- Formula application without drawing equivalent circuit
- Sign errors in dependent source handling
- Missing Thevenin equivalent circuit diagram
Earns more
- Correct handling of dependent source 2V_ab
- Explicit statement of maximum power transfer condition R_L = R_th
- Clear step-by-step nodal or mesh analysis
- Final values with correct units
Extra mark
- Verification of power balance in the circuit
- Alternative method check for R_th calculation
- (b(i)) Definitions of input bias current and offset voltage; inverting amp circuit with gain -4 minimizing bias. 10 marks
define— precise definition → the distinguishing feature → one example
Must cover
- Precise definition of input bias current
- Precise definition of input offset voltage
- Inverting amplifier circuit with gain = -4
- Compensation resistor to minimize bias current effect
Loses marks
- Missing compensation resistor in circuit
- Incorrect gain calculation or resistor values
- Vague or incomplete definitions
Earns more
- Correct placement of compensation resistor at non-inverting input
- Labelled circuit diagram with all components
- Explanation of how compensation minimizes bias effect
- Correct resistor values for gain -4
Extra mark
- Mention of typical bias current values for common op-amps
- Note on offset voltage compensation techniques
- (b(ii)) Output voltage adjustment range and maximum power dissipation in T_1 for worst case. 10 marks
calculate— given → formula → substitution → result with units → interpretation
Must cover
- Calculate minimum output voltage from circuit parameters
- Calculate maximum output voltage from circuit parameters
- Determine worst-case conditions for T_1 power dissipation
- Calculate maximum power dissipation in T_1
Loses marks
- Ignoring input voltage range in calculations
- Incorrect worst-case condition identification
- Missing power dissipation formula application
Earns more
- Correct use of 12V Zener reference voltage
- Proper analysis of voltage divider network
- Consideration of input voltage range 15V to 20V
- Clear identification of worst-case scenario
Extra mark
- Discussion of thermal considerations for T_1
- Note on stability of the regulated output
- (c) Determine the function performed by the three 2-input multiplexer circuit. 10 marks
describe— define → structure or process in order → labelled diagram → significance
Must cover
- Analyze each MUX's input-output relationship
- Determine Z_1 and Z_2 expressions in terms of inputs
- Determine final output Z expression
- Identify the overall circuit function
Loses marks
- Incorrect MUX output expressions
- Missing logical simplification steps
- Failure to identify the overall function
Earns more
- Truth table or logical expression derivation
- Clear step-by-step MUX analysis
- Correct identification of multiplexer function
- Proper use of select lines S_0 and S_1
Extra mark
- Comparison with standard multiplexer configurations
- Note on practical applications of this function
Model answer coming soon
Every evaluation on this site is marked against a verified model answer. This question's answer is still being written; evaluation opens the moment it lands.
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