Paper I — Q3
(a) Determine the time signal that corresponds to the following bilateral Laplace transform and the ROCs given below by using the…
Determine the time signal that corresponds to the following bilateral Laplace transform and the ROCs given below by using the method of partial fractions:
X(s) = (4s² + 8s + 10)/((s+2)(s² + 2s + 5))
With ROC Re(s) < -2
With ROC Re(s) > -1
With ROC -2 < Re(s) < -1
Explain the working of the given OPAMP circuit. Draw the output waveforms at points A and B showing the time and voltage.
Given that, V_Z₁ = V_Z₂ = 3.3 V, C₁ = 1 muF, the power supply voltage to OPAMPs is ± 12 V and R₁ = R₂ = R₃ = R₄ = R₅ = R₆ = 2 kΩ :
Suggest to replace suitable resistances so that the output voltages at A and B are having swing of ± 6 V and the output frequency is fixed to 500 Hz.
Find the logic equations for the outputs in the concise form and write the corresponding truth table for the circuit given below :
हिंदी में प्रश्न पढ़ें
नीचे दिए गए द्विपक्षीय लाप्लास रूपांतर और ROCs के अनुरूप समय संकेत, आंशिक भिन्न विधि प्रयोग करते हुए ज्ञात कीजिए :
X(s) = (4s² + 8s + 10)/((s+2)(s² + 2s + 5))
ROC Re(s) < -2 के साथ
ROC Re(s) > -1 के साथ
ROC -2 < Re(s) < -1 के साथ
दिए गए OPAMP परिपथ की कार्यप्रणाली की व्याख्या कीजिए। समय व बोल्टता प्रदर्शित करते हुए बिंदु A तथा B पर निर्गत तरंग रूप आरेखित कीजिए।
दिया गया है, V_Z₁ = V_Z₂ = 3.3 V, C₁ = 1 muF, OPAMP को प्रदत्त शक्ति प्रदाय बोल्टता ± 12 V है तथा R₁ = R₂ = R₃ = R₄ = R₅ = R₆ = 2 kΩ है :
उपयुक्त प्रतिरोधों में बदलाव प्रस्तावित कीजिए ताकि A और B पर निर्गत बोल्टता परास ± 6 V हो जाए तथा निर्गत आवृत्ति 500 Hz हो जाए।
नीचे दिए गए परिपथ के आउटपुट के लिए संक्षिप्त तार्किक समीकरण निकालिए और तदनुरूप सत्य-सारणी लिखिए :
The figure this question refers to, in words
The question paper is a scan and the diagram did not survive as text. This is the figure as read from the original page — every component, value and label — so the question can be worked from the text below.
(b) An electronic circuit diagram consisting of three operational amplifiers (OPAMPs) labeled I1, I2, and I3, and two Zener diodes labeled Z1 and Z2. The circuit is powered by a supply voltage (implied +/-12V).
- OPAMP I1 is configured as a comparator. Its non-inverting input (+) is connected to a node formed by resistors R1 and R2. R1 is connected to the output of OPAMP I2 (labeled point A). R2 is connected to the output of OPAMP I3 (labeled point B). The inverting input (-) of I1 is connected to ground. The output of I1 is connected to a node labeled D via resistor R3.
- Node D is connected to the anode of Zener diode Z1 (cathode to ground) and the cathode of Zener diode Z2 (anode to ground). This node D is also connected to the inverting input (-) of OPAMP I2 via resistor R4.
- OPAMP I2 is configured as an integrator. Its non-inverting input (+) is connected to ground. Its inverting input (-) is connected to node D via R4 and to its own output (point A) via capacitor C1. The output is labeled A.
- The output of OPAMP I2 (point A) is also connected to the non-inverting input (+) of OPAMP I3.
- OPAMP I3 is configured as a comparator. Its inverting input (-) is connected to a voltage divider formed by resistors R5 and R6. R5 is connected to ground, and R6 is connected to the output of I3 (point B). The junction of R5 and R6 connects to the inverting input. The output is labeled B.
All components are labeled with their reference designators (R1-R6, C1, Z1, Z2, I1-I3) and nodes (A, B, D).
(c) A logic circuit diagram with two inputs, D0 and D1, and four outputs, Y0, Y1, Y2, and Y3 (all with overbars indicating active-low or inverted outputs). The circuit consists of four 2-input NAND gates. The inputs D0 and D1 are connected to the gates as follows: 1. The top gate (output Y0) has inputs D0 and D1. 2. The second gate (output Y1) has inputs D0 and the output of the third gate. 3. The third gate (output Y2) has inputs D1 and the output of the fourth gate. 4. The bottom gate (output Y3) has inputs D0 and D1. The outputs of the third and fourth gates are also fed back into the second and third gates respectively, creating a cross-coupled structure. The specific connections are: D0 and D1 go to the top gate. D0 and the output of the bottom gate go to the second gate. D1 and the output of the third gate go to the third gate. D0 and D1 go to the bottom gate. The outputs are labeled Y0, Y1, Y2, Y3 from top to bottom.
Model answer
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(a) Inverse bilateral Laplace transform
Partial fractions:
X(s) = A/(s + 2) + (Bs + C)/(s² + 2s + 5), so 4s² + 8s + 10 = A(s² + 2s + 5) + (Bs + C)(s + 2).
- s = −2: 16 − 16 + 10 = 5A, so A = 2
- s² terms: 4 = A + B, so B = 2
- s terms: 8 = 2A + 2B + C = 8 + C, so C = 0 (constant term check: 5A + 2C = 10 ✓)
Writing s² + 2s + 5 = (s + 1)² + 2² and 2s = 2(s + 1) − 2:
X(s) = 2/(s + 2) + 2(s + 1)/[(s + 1)² + 4] − 2/[(s + 1)² + 4]
Poles: s = −2 and s = −1 ± j2. Transform pairs used (a pole to the left of the ROC gives a right-sided term; a pole to the right of the ROC gives a left-sided term with a minus sign):
- 1/(s + 2) ↔ e^(−2t)u(t) for Re(s) > −2, or −e^(−2t)u(−t) for Re(s) < −2
- (s + 1)/[(s + 1)² + 4] ↔ e^(−t)cos2t u(t) for Re(s) > −1, or −e^(−t)cos2t u(−t) for Re(s) < −1
- 2/[(s + 1)² + 4] ↔ e^(−t)sin2t u(t) for Re(s) > −1, or −e^(−t)sin2t u(−t) for Re(s) < −1
(i) ROC Re(s) < −2 (left of all poles, every term left-sided):
x(t) = −[2e^(−2t) + 2e^(−t)cos2t − e^(−t)sin2t] u(−t)
(ii) ROC Re(s) > −1 (right of all poles, every term right-sided):
x(t) = [2e^(−2t) + 2e^(−t)cos2t − e^(−t)sin2t] u(t)
(iii) ROC −2 < Re(s) < −1 (right of −2, left of −1 ± j2):
x(t) = 2e^(−2t)u(t) − [2e^(−t)cos2t − e^(−t)sin2t] u(−t)
Only case (ii) is causal, and since its ROC contains the jω-axis it is also stable; cases (i) and (iii) are non-causal and, as their ROCs exclude the jω-axis, unstable.
(b) Op-amp triangular/square-wave generator
Reading the circuit:
- I₁ has its inverting input grounded and its non-inverting input fed from R₁ (from output A) and R₂ (from node D). It is a non-inverting Schmitt trigger: its output is at +V_sat or −V_sat depending on the sign of V₊ = (R₂V_A + R₁V_D)/(R₁ + R₂).
- R₃ and the back-to-back Zeners Z₁, Z₂ clamp node D to ±V_D, where V_D = V_Z + V_F ≈ 3.3 + 0.7 = 4.0 V (one Zener in breakdown, the other forward-biased). R₃ limits the Zener current to about (12 − 4)/2 kΩ ≈ 4 mA.
- I₂ with R₄ and C₁ is an inverting integrator: dV_A/dt = −V_D/(R₄C₁).
- I₃ takes the square wave at D on its non-inverting input and, with R₅ and R₆ as the gain-setting resistors (as the question intends), amplifies it by (1 + R₆/R₅) = 2. So B is a square wave, not a copy of A.
Working: when D = +V_D, A ramps down. V₊ stays positive until R₂V_A + R₁V_D = 0, i.e. V_A = −(R₁/R₂)V_D. At that instant I₁ switches to −V_sat, D becomes −V_D, and A ramps up until V_A = +(R₁/R₂)V_D, when I₁ switches back. The loop therefore oscillates on its own.
- Peak of the triangle at A: V_Ap = (R₁/R₂)V_D = 1 × 4 = ±4 V
- Square wave at B: ±(1 + R₆/R₅)V_D = ±8 V (B is high while A is falling)
- Half period: the ramp covers 2V_Ap at a slope V_D/(R₄C₁), so T/2 = 2(R₁/R₂)R₄C₁ and T = 4(R₁/R₂)R₄C₁ = 4 × 1 × 2 kΩ × 1 µF = 8 ms, f = 125 Hz. The frequency does not depend on the Zener voltage.
Changes for ±6 V at A and B and f = 500 Hz (keeping R₂ = R₅ = 2 kΩ and C₁ = 1 µF):
- Output A: (R₁/R₂) × 4 = 6, so R₁/R₂ = 1.5 and R₁ = 3 kΩ.
- Output B: (1 + R₆/R₅) × 4 = 6, so R₆/R₅ = 0.5 and R₆ = 1 kΩ.
- Frequency: f = R₂/(4R₁R₄C₁) = 500 Hz gives R₄ = 1/(4 × 1.5 × 10⁻⁶ × 500) = 333 Ω (use 330 Ω).
If the Zener forward drop is ignored (V_D = 3.3 V), the same method gives R₁/R₂ = 6/3.3 = 1.82 (R₁ ≈ 3.64 kΩ), R₆/R₅ = 0.82 (R₆ ≈ 1.64 kΩ) and R₄ = 1/(4 × 1.82 × 10⁻⁶ × 500) = 275 Ω. Note also that, if the I₃ stage is read literally as drawn (the R₅–R₆ junction tied to B), it is a voltage follower and B = V_D; ±6 V at B would then need Zeners of about 5.3 V instead of a resistor change.
(c) Logic equations and truth table
The first NAND gives N = (D₀D₁)′, which is also brought out as Ȳ₃. The top-right gate has three inputs: N, Ȳ₁ and Ȳ₂.
- Ȳ₃ = (D₀D₁)′
- Ȳ₁ = (D₀·N)′ = [D₀(D₀′ + D₁′)]′ = (D₀D₁′)′ = D₀′ + D₁
- Ȳ₂ = (D₁·N)′ = [D₁(D₀′ + D₁′)]′ = (D₀′D₁)′ = D₀ + D₁′
- Ȳ₀ = (N·Ȳ₁·Ȳ₂)′. Since (D₀′ + D₁′)(D₀′ + D₁) = D₀′ and D₀′(D₀ + D₁′) = D₀′D₁′, Ȳ₀ = (D₀′D₁′)′ = D₀ + D₁
Concise form (with D₁ as the MSB, mᵢ the minterms): Ȳ₀ = m₀′, Ȳ₁ = m₁′, Ȳ₂ = m₂′, Ȳ₃ = m₃′.
Truth table (D₁ D₀ → Ȳ₀ Ȳ₁ Ȳ₂ Ȳ₃):
- 0 0 → 0 1 1 1
- 0 1 → 1 0 1 1
- 1 0 → 1 1 0 1
- 1 1 → 1 1 1 0
Exactly one output is LOW for each input combination, so the circuit is a 2-to-4 line decoder with active-low outputs.
How this answer will be evaluated
What earns full marks: Complete working with correct results, clear diagrams, and proper justification for all parts.
Evaluation rubric
Each sub-part is marked on its own, against the marks and word limit printed on the paper.
- (a) Find x(t) for X(s) = (4s² + 8s + 10)/[(s + 2)(s² + 2s + 5)] for the three ROCs using partial fractions. 20 marks
calculate— given → formula → substitution → result with units → interpretation
Must cover
- Partial fractions: X(s) = 2/(s + 2) + 2s/(s² + 2s + 5) = 2/(s + 2) + 2(s + 1)/[(s + 1)² + 4] − 2/[(s + 1)² + 4]
- Poles at −2 and −1 ± j2; rule: ROC to the right of a pole gives a right-sided term, to the left a left-sided term with a minus sign
- (i) Re(s) < −2: x(t) = −[2e^(−2t) + 2e^(−t)cos2t − e^(−t)sin2t]u(−t); (ii) Re(s) > −1: x(t) = [2e^(−2t) + 2e^(−t)cos2t − e^(−t)sin2t]u(t)
- (iii) −2 < Re(s) < −1: x(t) = 2e^(−2t)u(t) − [2e^(−t)cos2t − e^(−t)sin2t]u(−t)
Loses marks
- Wrong partial-fraction coefficients
- Sign error for left-sided terms
Earns more
- Remark on causality/stability of each case (only (ii) is causal and stable)
- Coefficient check
Extra mark
- Pole–zero plot with ROC shading
- (b) Explain the op-amp circuit, sketch waveforms at A and B, and choose resistors for ±6 V swing at 500 Hz. 20 marks
explain— definition/context → points in order → small example → short close
Must cover
- I₁ is a non-inverting Schmitt trigger comparing a weighted sum of V_A and V_D with 0; D is clamped by the back-to-back Zeners to ±(V_Z + V_F) ≈ ±4 V; I₂ is an inverting integrator; I₃ amplifies the square wave at D
- Waveforms: A is a triangle of peak (R₁/R₂)V_D = ±4 V; B is a square wave (±8 V with gain 1 + R₆/R₅ = 2); B high while A falls
- Period T = 4(R₁/R₂)R₄C₁ = 8 ms, f = 125 Hz for the given values
- Design: R₁ = 3 kΩ (R₁/R₂ = 1.5) for ±6 V at A, R₆ = 1 kΩ (gain 1.5) for ±6 V at B, R₄ = 333 Ω for 500 Hz
Loses marks
- Treating B as a triangle
- Inverting the threshold ratio (using R₂/R₁)
Earns more
- R₃ limits Zener current ((12 − 4)/2k ≈ 4 mA)
- Notes the result if Zener forward drop is ignored (±3.3 V basis)
Extra mark
- Comments on the drawn I₃ connection acting as a follower
- (c) Find the concise logic equations and truth table of the given NAND circuit. 10 marks
derive— given → assumptions → stepwise derivation → result → check
Must cover
- N = (D₀D₁)′ = Ȳ₃
- Ȳ₁ = (D₀·N)′ = D₀′ + D₁; Ȳ₂ = (D₁·N)′ = D₀ + D₁′
- Ȳ₀ = (N·Ȳ₁·Ȳ₂)′ (three-input NAND) = (D₀′D₁′)′ = D₀ + D₁
- Truth table showing exactly one output LOW for each input: an active-low 2-to-4 decoder
Loses marks
- Treating the output gate as 2-input (giving XOR)
- Truth table inconsistent with equations
Earns more
- Minterm notation Ȳᵢ = mᵢ′
- Identifies D₁ as MSB
Extra mark
- Gate-count comparison with a standard decoder
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