Paper II — Q1
(a) What are the limitations of (i) Proportional (P), (ii) Integral (I), (iii) Derivative (D), and (iv) PID Controllers? What is…
What are the limitations of (i) Proportional (P), (ii) Integral (I), (iii) Derivative (D), and (iv) PID Controllers? What is the application of positive feedback control system? 10 marks
Explain the operation performed by 8085 microprocessor when the following arithmetic instructions are executed: (i) ADD M (ii) ADC M (iii) DAD rp (iv) SBI d8 (v) DCR reg (5×2=10 marks)
The ohmmeter circuit has V_B = 1·5 V, R_1 = 15 kΩ, R_m = 50 Ω, R_2 = 50 Ω and meter FSD = 50 μA. Determine the ohmmeter scale reading at 0·5 FSD.
Calculate the power loss in a cable insulation having capacitance 9 μF, loss angle 0.05 degree and operating at 11 kV, 50 Hz. Draw the phasor diagram and equivalent circuit also.
Explain the concept of a constellation diagram. Draw the PSK signal constellations for the value of M = 2, 4 and 8, if all have same transmitted signal energy E_s.
हिंदी में प्रश्न पढ़ें
समानुपाती (P), (ii) समाकलित (I), (iii) व्युत्पन्न (D), एवं (iv) PID नियंत्रकों की क्या सीमाएं हैं? धनात्मक प्रतिपुष्टि नियंत्रण पद्धति का क्या अनुप्रयोग है?
जब एक 8085 सूक्ष्म संसाधित्र को निम्नलिखित अंकगणितीय निर्देश दिए जाते हैं, तो इसके द्वारा की जाने वाली क्रियाविधि की व्याख्या कीजिए: (i) ADD M (ii) ADC M (iii) DAD rp (iv) SBI d8 (v) DCR reg
ओममीटर परिपथ में V_B = 1·5 V, R_1 = 15 kΩ, R_m = 50 Ω, R_2 = 50 Ω एवं मीटर FSD = 50 μA हैं। 0·5 FSD के लिए ओममीटर के पैमाने के पठन को निर्धारित कीजिए।
9 μF धारिता, 0·05 अंश हास कोण एवं 11 kV, 50 Hz पर कार्यरत एक केबल अचालक (विद्युतरोधन) में शक्ति हास की गणना कीजिए। कल्पीय (फेजर) आरेख एवं समकक्ष परिपथ भी आरेखित कीजिए।
नक्षत्र आरेख (कांस्टेलेशन डायग्राम) की संकल्पना की व्याख्या कीजिए। यदि सभी संकेतों की प्रेषित ऊर्जा E_s एकसमान हो, तो M = 2, M = 4 एवं M = 8 के मान के लिए PSK संकेत नक्षत्र का आरेखण कीजिए।
The figure this question refers to, in words
The question paper is a scan and the diagram did not survive as text. This is the figure as read from the original page — every component, value and label — so the question can be worked from the text below.
(c) A circuit diagram for an ohmmeter. A DC voltage source labeled V_B is connected in series with a variable resistor labeled R_x. The terminals of R_x are labeled A and B. From terminal B, the circuit continues to a fixed resistor R_1. After R_1, the circuit splits into two parallel branches. The first branch contains a variable resistor R_2. The second branch contains a fixed resistor R_m in series with a meter labeled M. The current entering the parallel section is labeled I_b. The current through the R_2 branch is labeled I_2. The current through the meter branch is labeled I_m. The voltage across the parallel combination of R_2 and the (R_m + M) branch is labeled V_m. The bottom of the voltage source, the bottom of R_2, and the bottom of the meter M are all connected to a common ground line.
Model answer
Drafted with AI by UPSC Answer Check against this question's marking rubric, to the expected length. UPSC does not publish answers for Mains — this is one way to score well, not an official key. How we build rubrics and answers.
(a) Limitations of P, I, D and PID controllers; applications of positive feedback
(i) Proportional (P) control, u = K_p e
- It leaves a steady-state error (offset) for a step input in a type-0 loop, e_ss = 1/(1 + K_pK), because some error is needed to hold the controller output. It cannot remove the offset caused by a constant load disturbance.
- Raising K_p to cut the offset reduces damping, increases overshoot and can make a third- or higher-order loop unstable.
(ii) Integral (I) control, u = K_i ∫e dt
- It adds a pole at the origin (90° phase lag), so the response becomes slower and more oscillatory and relative stability falls.
- If the actuator saturates while the error persists, the integrator keeps charging (integral wind-up). This produces a large overshoot when the loop recovers.
- It acts slowly on sudden changes, because its output depends on the accumulated error.
(iii) Derivative (D) control, u = K_d de/dt
- It gives no output for a constant error, so it cannot remove steady-state error and is never used alone.
- Its gain rises with frequency, so it amplifies measurement noise and needs a filter, K_d s/(1 + τs).
- A step change in set-point produces a derivative "kick" that can saturate the actuator.
(iv) PID control
- Three interacting gains must be tuned (Ziegler–Nichols, Cohen–Coon or trial), and they need retuning when plant parameters change.
- It inherits both noise sensitivity (D) and wind-up (I), so practical controllers need anti-windup and derivative filtering.
- As a fixed, linear, single-loop law it performs poorly on strongly nonlinear, time-varying or long dead-time processes.
Applications of positive feedback. Positive feedback raises loop gain and reduces stability, so it is used where regeneration or switching is wanted:
- Oscillators (RC phase-shift, Wien-bridge, LC): sustained oscillation when the Barkhausen condition holds, loop gain Aβ = 1 with 0° (360°) loop phase.
- Schmitt triggers and comparators with hysteresis, bistable and astable multivibrators, and latches (flip-flops, the two-transistor thyristor model).
- Regenerative amplifiers and receivers, which increase gain; voltage build-up of a self-excited DC generator.
- Positive current feedback (IR compensation) in DC drives, which offsets the speed drop caused by armature resistance.
(b) 8085 arithmetic instructions
(i) ADD M: (A) ← (A) + [(HL)] The byte at the memory address held in HL is added to the accumulator, and the result stays in A. It uses register-indirect addressing and is 1 byte long, taking 2 machine cycles (opcode fetch, memory read) and 7 T-states. All five flags (S, Z, AC, P, CY) are set by the result. Example: A = 35H, HL = 2050H, [2050H] = 49H gives A = 7EH, with CY = 0, Z = 0, S = 0, AC = 0 and P = 1 (six 1s).
(ii) ADC M: (A) ← (A) + [(HL)] + CY The same memory byte and the carry flag are added to A. It is 1 byte long and takes 7 T-states, and all flags are affected. It is used for multi-byte addition: add the low bytes with ADD, then the higher bytes with ADC so the carry propagates.
(iii) DAD rp: (HL) ← (HL) + (rp), with rp = BC, DE, HL or SP This is a 16-bit addition of the register pair to HL, with the result left in HL. It is 1 byte long, taking 3 machine cycles (opcode fetch plus two bus-idle cycles) and 10 T-states. Only CY is affected, set by a carry out of bit 15. DAD H doubles HL, which acts as a 16-bit left shift.
(iv) SBI d8: (A) ← (A) − d8 − CY The 8-bit immediate data and the borrow (CY) are subtracted from A, with the result left in A. It is 2 bytes long, taking 2 machine cycles (opcode fetch, memory read of d8) and 7 T-states. All flags are affected, and CY = 1 indicates a borrow. It is used for multi-byte subtraction.
(v) DCR reg: (reg) ← (reg) − 1 The selected 8-bit register (B, C, D, E, H, L or A) is decremented by one. It is 1 byte long, taking 1 machine cycle and 4 T-states. S, Z, AC and P are affected, but CY is not changed. A typical use is as a loop counter: DCR C followed by JNZ.
(c) Ohmmeter reading at 0.5 FSD
Circuit. Rx is in series with V_B and R₁. The meter (R_m = 50 Ω) is shunted by the zero-adjust resistor R₂ = 50 Ω.
At 0.5 FSD: I_m = 0.5 × 50 μA = 25 μA V_m = I_mR_m = 25×10⁻⁶ × 50 = 1.25 mV I₂ = V_m/R₂ = 1.25 mV/50 Ω = 25 μA I_b = I_m + I₂ = 50 μA
Total resistance: R_total = V_B/I_b = 1.5/(50×10⁻⁶) = 30 000 Ω
Internal resistance: R_in = R₁ + R_m‖R₂ = 15 000 + 25 = 15 025 Ω
Scale reading: R_x = R_total − R_in = 30 000 − 15 025 = 14 975 Ω ≈ 15 kΩ
Checks. With Rx = 0, I_b = 1.5/15 025 = 99.8 μA and I_m = 49.9 μA ≈ FSD, so the scale zero sits at full deflection. The half-scale reading always equals the internal resistance R₁ + R_m‖R₂. The scale is non-linear: 0.25 FSD reads 44.98 kΩ and 0.75 FSD reads 4.98 kΩ.
(d) Power loss in cable insulation
Equivalent circuit. A lossy dielectric behaves as an ideal capacitor C in parallel with a high resistance R. The capacitive current I_C leads V by 90°. The small resistive current I_R is in phase with V and produces the heat. The total current leads V by φ = 90° − δ, where δ is the loss angle.
Calculation. ω = 2π × 50 = 314.16 rad/s; tan δ = tan 0.05° = 8.727×10⁻⁴ I_C = ωCV = 314.16 × 9×10⁻⁶ × 11 000 = 31.10 A I_R = I_C tan δ = 31.10 × 8.727×10⁻⁴ = 27.1 mA P = VI_R = V²ωC tan δ = (11 000)² × 314.16 × 9×10⁻⁶ × 8.727×10⁻⁴ = 298.6 W Equivalent loss resistance R = V/I_R = 11 000/0.02714 ≈ 405 kΩ. The insulation power factor is cos φ = sin δ ≈ 8.7×10⁻⁴.
(e) Constellation diagram and PSK constellations
Concept. A constellation diagram is the signal-space picture of a digital modulation. Each of the M symbols is written on two orthonormal basis functions, φ₁(t) = √(2/T) cos 2πf_ct and φ₂(t) = √(2/T) sin 2πf_ct, and plotted as a point (s_i1, s_i2). The distance of a point from the origin is √(symbol energy), and its angle is the carrier phase. The distance between points decides how easily noise causes one symbol to be mistaken for another, so the minimum distance d_min sets the error probability. Measured constellations are also used to diagnose noise, phase error and distortion (error vector magnitude).
M-PSK with equal energy Es. s_i(t) = √(2Es/T) cos(2πf_ct + θ_i) with θ_i = 2π(i − 1)/M. All points lie on a circle of radius √Es, and d_min = 2√Es sin(π/M).
- M = 2 (BPSK): two points at ±√Es on φ₁ (0° and 180°); d_min = 2√Es; 1 bit per symbol.
- M = 4 (QPSK): four points 90° apart (drawn at 45°, 135°, 225° and 315°); d_min = √2·√Es = 1.41√Es; 2 bits per symbol.
- M = 8 (8-PSK): eight points 45° apart; d_min = 2√Es sin 22.5° = 0.765√Es; 3 bits per symbol.
Consequence. For the same Es, a larger M carries more bits per symbol (log₂M) in the same bandwidth, but the points crowd together and the error rate rises. Per bit, BPSK and QPSK have the same error performance, while 8-PSK needs about 3.6 dB more Eb/N₀ than QPSK.
How this answer will be evaluated
What earns full marks: All parts answered with correct method, diagrams, and calculations; no errors in formulas or units.
Evaluation rubric
Each sub-part is marked on its own, against the marks and word limit printed on the paper.
- (a) State the limitations of P, I, D and PID controllers and the applications of positive feedback. 10 marks
discuss— intro → 3-4 dimensions → example → balanced close
Must cover
- P: steady-state offset e_ss = 1/(1 + K_pK) for type-0 loops; higher K_p reduces damping and can destabilise
- I: pole at origin adds 90° lag, slower and more oscillatory response; integral wind-up on actuator saturation
- D: no action on constant error so cannot be used alone; amplifies high-frequency noise; derivative kick
- PID: three interacting gains to tune; inherits noise and wind-up problems; fixed linear law struggles with nonlinear, time-varying or dead-time plants
- Positive feedback: oscillators (Barkhausen Aβ = 1, 0° loop phase), Schmitt trigger/hysteresis, multivibrators and latches, regenerative amplification
Loses marks
- Saying integral action improves stability
- Omitting the application of positive feedback
Earns more
- Anti-windup and derivative filtering as remedies
- Positive current feedback (IR compensation) in drives or self-excitation of DC generators
Extra mark
- Transfer functions of each controller
- (b) Explain what the 8085 does for ADD M, ADC M, DAD rp, SBI d8 and DCR reg. 10 marks
explain— definition/context → points in order → small example → short close
Must cover
- ADD M: A ← A + [HL]; register indirect; 1 byte, 7 T-states; all five flags affected
- ADC M: A ← A + [HL] + CY; used for multi-byte addition; all flags
- DAD rp: HL ← HL + rp (BC, DE, HL, SP); 10 T-states; only CY affected
- SBI d8: A ← A − d8 − CY; 2-byte immediate, 7 T-states; all flags (CY = borrow)
- DCR reg: reg ← reg − 1; 4 T-states; S, Z, AC, P affected, CY unchanged
Loses marks
- Saying DAD affects all flags
- Saying DCR changes CY
- Omitting the carry in ADC/SBI
Earns more
- Machine cycles listed (OF, MR, bus idle)
- Worked example with flag values
Extra mark
- Typical use: DCR with JNZ as loop counter; DAD H as 16-bit shift
- (c) Find the ohmmeter scale reading at 0.5 FSD for V_B = 1.5 V, R₁ = 15 kΩ, R_m = 50 Ω, R₂ = 50 Ω, FSD 50 μA. 10 marks
calculate— given → formula → substitution → result with units → interpretation
Must cover
- At 0.5 FSD, I_m = 25 μA; V_m = 1.25 mV; I₂ = 25 μA; I_b = 50 μA
- Internal resistance R₁ + R_m‖R₂ = 15 025 Ω
- R_total = 1.5/50 μA = 30 kΩ
- R_x = 30 000 − 15 025 = 14 975 Ω ≈ 15 kΩ
Loses marks
- Ignoring the shunt current
- Taking I_b = I_m
Earns more
- Notes half-scale reading equals internal resistance
- R₂ is the zero-adjust shunt; Rx = 0 gives ≈ FSD
Extra mark
- Readings at 0.25 and 0.75 FSD showing non-linear scale
- (d) Calculate the dielectric loss for C = 9 μF, δ = 0.05°, 11 kV, 50 Hz and draw the phasor diagram and equivalent circuit. 10 marks
calculate— given → formula → substitution → result with units → interpretation
Must cover
- Parallel equivalent circuit: ideal C with loss resistance R
- Phasor diagram: I_R in phase with V, I_C leading by 90°, I leading V by 90° − δ
- P = V²ωC tan δ; tan 0.05° = 8.727×10⁻⁴
- I_C = 31.1 A, I_R = 27.1 mA, P = 298.6 W
Loses marks
- Using cos δ instead of tan δ
- δ in radians as 0.05
- No diagrams
Earns more
- R = V/I_R ≈ 405 kΩ
- Insulation power factor = sin δ ≈ tan δ
Extra mark
- Series equivalent circuit mentioned
- (e) Explain the constellation diagram and draw PSK constellations for M = 2, 4 and 8 at equal symbol energy Es. 10 marks
explain— definition/context → points in order → small example → short close
Must cover
- Signal-space plot on orthonormal basis φ₁ (cos) and φ₂ (sin); distance from origin = √(symbol energy), angle = phase
- M-PSK points at θ_i = 2π(i − 1)/M on a circle of radius √Es
- BPSK: ±√Es, d_min = 2√Es; QPSK: 90° apart, d_min = √2·√Es; 8-PSK: 45° apart, d_min = 0.765√Es
- Labelled constellation sketches for all three
Loses marks
- Different radii for different M
- Points not equally spaced
Earns more
- d_min = 2√Es sin(π/M) and link to error probability
- Gray-coded bit mapping
Extra mark
- Per-bit comparison: 8-PSK needs about 3.6 dB more Eb/N0 than QPSK
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