(a) Calculate the real and reactive power at sending end of a transmission line while delivering 10 MVA load at 0·85 lagging…

(a) Sending-end real and reactive power

Nature of the line. For a passive reciprocal line, AD − BC = 1. With A = D = 1 this gives BC = 0, so C = 0. The line is a short line with only the series impedance B, and I_S = I_R.

Receiving end. S_R = 10 MVA at 0.85 lagging: P_R = 8.5 MW; Q_R = 10 × sin(cos⁻¹0.85) = 10 × 0.5268 = 5.268 MVAr V_R = 33/√3 = 19.053 kV per phase (reference) I_R = 10×10⁶/(√3 × 33×10³) = 174.96 A, at −31.79°

Line impedance. B = 12.12∠64.64° Ω, so R = 12.12 cos 64.64° = 5.191 Ω and X = 12.12 sin 64.64° = 10.952 Ω.

Line losses (three-phase). 3I²R = 3 × 174.96² × 5.191 = 0.477 MW 3I²X = 3 × 174.96² × 10.952 = 1.006 MVAr

Sending end. P_S = 8.5 + 0.477 = 8.977 MW Q_S = 5.268 + 1.006 = 6.274 MVAr (lagging)

Check through V_S. V_S = V_R + I_R R + jI_R X = 19 053 + (772 − j478) + (1009 + j1629) = 20 834 + j1150 V = 20.87 kV per phase at δ = 3.16°, which is 36.14 kV line. S_S = 3V_SI_S* = 8.977 + j6.274 MVA, confirming the result. The sending-end power factor is 8.977/10.95 = 0.82 lagging, and the voltage regulation is (20.87 − 19.05)/19.05 = 9.5%.

(b)(i) Maximum bit rate for non-coherent ASK

Received power. 80 dB loss is a factor of 10⁸: P_R = 0.3/10⁸ = 3×10⁻⁹ W

Noise. Two-sided PSD N₀/2 = 10⁻¹⁵ W/Hz, so N₀ = 2×10⁻¹⁵ W/Hz.

Error probability. Take 300 mW as the average transmitted power, so E_b = P_RT_b is the average energy per bit. For on-off keying with envelope detection at high SNR: P_e ≈ ½ exp(−E_b/2N₀)

Required energy. ½ exp(−E_b/2N₀) ≤ 10⁻⁴ ⇒ E_b/2N₀ ≥ ln(5000) = 8.517 E_b ≥ 17.03 × 2×10⁻¹⁵ = 3.41×10⁻¹⁴ J

Maximum bit rate. R_b = P_R/E_b = 3×10⁻⁹/3.41×10⁻¹⁴ = 8.8×10⁴ bit/s ≈ 88 kbit/s If 300 mW were instead the power during a "1" pulse, the average energy would be half as large, and the rate would fall to about 44 kbit/s. Coherent ASK would allow a somewhat higher rate for the same P_e.

(b)(ii) PCM: minimum n, sampling rate and bit rate

Step size. The dynamic range is 2 V (peak-to-peak). The maximum quantisation error is half a step, so Δ/2 ≤ 0.01 × 2 V = 0.02 V ⇒ Δ ≤ 0.04 V

Number of bits. L = 2/Δ ≥ 50 levels. 2⁵ = 32 is too few, so n = 6 (64 levels). Check: Δ = 2/64 = 0.03125 V, and the maximum error is 0.0156 V = 0.78% of the range, within 1%.

Sampling rate. f_s,min = 2 × 8 kHz = 16 kHz (16 000 samples/s).

Bit rate. R_b = n f_s = 6 × 16 000 = 96 kbit/s. The minimum transmission bandwidth is R_b/2 = 48 kHz, and the SQNR for a full-scale sinusoid is about 6.02 × 6 + 1.76 ≈ 38 dB.

(c)(i) Raising the voltage and current ratings of an HVDC converter station

Voltage rating

• Connect many thyristors in series in each valve, with RC damping circuits and grading capacitors for equal static and transient voltage sharing, plus a few redundant thyristor levels.
• Use higher-voltage thyristors (up to about 8.5 kV per device) and multi-tier valve stacks with proper insulation coordination, bushings and clearances.
• Connect 6-pulse bridges in series to form 12-pulse groups, and series groups per pole. Operate bipolar (±V_d) to double the line voltage for a given insulation level to earth.
• In VSC (MMC) stations, increase the number of series-connected submodules per arm.

Current rating

• Use larger-diameter thyristor wafers (5- and 6-inch devices carrying about 4–5 kA) instead of paralleling devices.
• Connect valves or complete converter groups in parallel where a single device rating is not enough.
• Use efficient de-ionised water cooling of the valves to raise the continuous and overload current.
• In VSC stations, use larger or paralleled press-pack IGBT modules. Light-triggered thyristors are widely used so that long series strings fire simultaneously and reliably.

(c)(ii) Requirements of HVDC valves

• Voltage withstand: high forward and reverse blocking voltage, including switching and lightning transients and high dv/dt, with uniform voltage sharing along the series string.
• Current capability: rated continuous current, specified overloads, and fault surge currents (commutation failure, short circuits) without damage; limited di/dt at turn-on, using saturable valve reactors.
• Firing: all series thyristors must fire simultaneously and reliably, through fibre-optic electrical or light triggering, with firing possible even at low voltage.
• Protection: forward-overvoltage protection (breakover-diode firing), surge arresters across valves, and a few redundant levels so one failed thyristor does not trip the pole.
• Losses and cooling: low conduction and switching losses, low reverse-recovery charge, and effective (water) cooling.
• Reliability and maintenance: monitoring of each thyristor level, fire-safe materials, seismic and mechanical strength, low electromagnetic interference, and easy replacement of components.