(a) The capacitance of a piezoelectric transducer is 2000 pF and charge sensitivity is 30 × 10⁻³ C/m. Assume the capacitance of…

(a) Piezoelectric transducer with cable and oscilloscope

Data. Charge sensitivity K_q = 30×10⁻³ C/m; C_t = 2000 pF; cable C_c = 150 pF; oscilloscope R = 1 MΩ in parallel with C_o = 100 pF.

Equivalent circuit. The crystal is a charge generator q = K_q x, which is equivalent to a current source i = K_q dx/dt. It drives all the capacitances in parallel with the oscilloscope resistance, so the output voltage is E₀/X = (K_q/C) · jωτ/(1 + jωτ), with C = C_t + C_c + C_o and τ = RC This is a high-pass characteristic: at high frequency the sensitivity is K_q/C, and at low frequency the charge leaks away through R.

(i) Sensitivity of the transducer alone (open-circuit voltage per unit displacement): S_t = K_q/C_t = 30×10⁻³/(2000×10⁻¹²) = 15×10⁶ V/m = 15 V/μm

(ii) High-frequency sensitivity of the whole system. C = 2000 + 150 + 100 = 2250 pF S_HF = K_q/C = 30×10⁻³/(2250×10⁻¹²) = 13.33×10⁶ V/m = 13.33 V/μm The cable and oscilloscope capacitances load the crystal and reduce the sensitivity by 11%.

(iii) Lowest frequency for 5% amplitude error. The amplitude ratio to the high-frequency value is ωτ/√(1 + ω²τ²). For 5% error: ωτ/√(1 + ω²τ²) = 0.95 ⇒ (ωτ)² = 0.9025/0.0975 = 9.256 ⇒ ωτ = 3.04 τ = RC = 10⁶ × 2250×10⁻¹² = 2.25 ms f = 3.04/(2π × 2.25×10⁻³) = 215 Hz

(iv) Shunt capacitance to extend the 5% range down to 20 Hz. The same ωτ = 3.04 is needed at 20 Hz: C_new = 3.04/(2π × 20 × 10⁶) = 24.2×10⁻⁹ F = 24.2 nF C_ext = 24.2 − 2.25 = 21.96 nF ≈ 22 nF, connected in parallel across the oscilloscope input. The price is sensitivity. The high-frequency sensitivity falls to K_q/C_new = 30×10⁻³/24.2×10⁻⁹ ≈ 1.24×10⁶ V/m, about one-eleventh of the original. A charge amplifier avoids this trade-off. (The Hindi version of the paper prints 20 kHz; the English version's 20 Hz is used here, since extending the range to 20 kHz would need no added capacitance.)

(b) Addressing modes of the 8085 instructions

• ADD reg: register addressing. The operand is in a register named in the opcode, and the accumulator is the implied destination: A ← A + r. It is 1 byte and 4 T-states. Example: ADD B.
• MOV rd, M: register indirect addressing. The operand's memory address is held in the HL pair (M = [HL]): rd ← [HL]. It is 1 byte and 7 T-states. Example: with HL = 2050H, MOV C, M copies [2050H] into C.
• CALL addr16: immediate addressing for the target (called direct addressing in some texts). The 16-bit subroutine address is carried in bytes 2 and 3 of the instruction. The CPU pushes the return address onto the stack using register-indirect addressing through SP, then loads PC with addr16. It is 3 bytes and 18 T-states (5 machine cycles). Example: CALL 2400H.
• LDA addr16: direct addressing. The instruction contains the 16-bit address of the operand: A ← [addr16]. It is 3 bytes and 13 T-states. Example: LDA 4200H.
• CMA: implied (implicit) addressing. No operand is written, because the accumulator is implied: A ← Ā (1's complement). It is 1 byte and 4 T-states, and no flags are affected.

The five 8085 addressing modes are immediate (MVI, LXI), register (MOV r1,r2, ADD r), direct (LDA, STA, IN, OUT), register indirect (MOV r,M, LDAX) and implied (CMA, RAL, STC).

(c) Parameters a and K of the first-order system

Response. With U(s) = 1/s: C(s) = K/[s(s + a)] = (K/a)[1/s − 1/(s + a)] c(t) = (K/a)(1 − e^(−at)) = (K/a)(1 − e^(−t/τ)), with τ = 1/a

Final value. c(∞) = lim s→0 of sC(s) = K/a. From Figure II, c(∞) = 2.0, so K/a = 2.

Time constant. The initial slope is c′(0) = K. The tangent from the origin, c = Kt, reaches the final value K/a at t = 1/a = τ. The figure shows this intersection at t = 0.2 s, so τ = 0.2 s. a = 1/τ = 5 s⁻¹ K = 2a = 10 (in s⁻¹, so that K/a is dimensionless)

Check. c(0.2) = 2(1 − e⁻¹) = 1.26, which is 63.2% of the final value, as expected at t = τ. The response settles within 2% in 4τ = 0.8 s.