(a) The open-loop transfer function of a feedback control system incorporating a dead time element is given by: G(s) = (Ke^(-Ts))/(s(s+1)) where K 0 and T 0 are variable scalar parameters. For a given value of T, show that the closed loop system

Question

(a) The open-loop transfer function of a feedback control system incorporating a dead time element is given by: G(s) = (Ke^(-Ts))/(s(s+1)) where K > 0 and T > 0 are variable scalar parameters. For a given value of T, show that the closed loop system for all values will be K < K₀ where K₀ = ω₀ cosec (ω₀T), and ω₀ is the smallest value of ω satisfying the equation ω = cot (ωT). (20 marks)

(b) (i) Compare I/O mapped I/O and memory mapped I/O interfacing techniques used in 8085 microprocessor. (10 marks)
(ii) What are the operating modes of Port-A of 8255? Explain handshake operation in I/O ports. (4+3+3=10 marks)

(c) In a parallel circuit, in one branch the current, I₁ = (100 ± 2) A and in the other branch the current, I₂ = (200 ± 5) A. Determine the total current considering the following errors: (i) Limiting error (ii) Probable error. Comment upon the results as well. (2+6+2=10 marks)

UPSC Answer Check · Accepted Answer

The directive 'compare' in part (b)(i) demands a structured contrast between I/O mapped and memory mapped I/O techniques, while parts (a), (b)(ii) and (c) require derivation, description and calculation respectively. Allocate approximately 40% effort to part (a) for the stability derivation, 30% to part (b) combined for interfacing concepts, and 30% to part (c) for error analysis. Structure with clear sub-headings for each part, presenting derivations stepwise, comparison in tabular format, and numerical results with proper significant figures.
- Part (a): Derivation of characteristic equation 1 + G(s) = 0, substitution of s = jω, separation into real and imaginary parts to obtain ω = cot(ωT), and final expression K₀ = ω₀ cosec(ω₀T) with justification for smallest ω₀
- Part (b)(i): Tabular comparison of I/O mapped vs memory mapped I/O covering address space (separate 8-bit vs shared 16-bit), control signals (IOR/IOW vs MEMR/MEMW), instruction set (IN/OUT vs LDA/STA), hardware complexity, and execution speed
- Part (b)(ii): Port-A operating modes (Mode 0-simple I/O, Mode 1-strobed I/O, Mode 2-bidirectional bus) with handshake signals (STB, IBF, INTR for input; OBF, ACK, INTR for output) and their timing sequence
- Part (c): Calculation of total current I = I₁ + I₂ = 300 A, limiting error as ±(2+5) = ±7 A, probable error as √(2²+5²) = ±5.39 A, and critical comment on error propagation in parallel circuits
- Critical analysis: Comment on why probable error gives tighter bounds than limiting error, and practical implications for instrument selection in power system measurements

Dimension	Weight	Max marks	Excellent	Average	Poor
Concept correctness	25%	2.5	Correctly identifies Nyquist stability criterion application for dead time systems in (a), accurately distinguishes I/O mapping fundamentals in (b)(i), precisely describes all three 8255 modes with correct handshake signal functions in (b)(ii), and properly applies error propagation formulas in (c)	Minor conceptual errors such as incorrect stability criterion choice, incomplete mode descriptions, or confusion between absolute and relative error propagation	Fundamental misconceptions like treating dead time as simple lag, confusing I/O mapped with memory mapped concepts, or applying series circuit error formulas to parallel circuit
Numerical accuracy	15%	1.5	Correctly computes probable error as √29 ≈ 5.39 A, limiting error as 7 A, and presents results with appropriate significant figures; handles transcendental equation in (a) with correct numerical interpretation	Correct final answers but with calculation errors in intermediate steps, or improper significant figure handling	Incorrect arithmetic such as adding errors in quadrature for limiting error, or order-of-magnitude mistakes in error propagation
Diagram quality	15%	1.5	Clear Nyquist plot sketch for part (a) showing encirclement condition, well-labelled 8255 handshake timing diagrams for Mode 1/Mode 2 in (b)(ii), and proper circuit diagram for parallel branches in (c)	Diagrams present but lacking labels, proper scaling, or missing critical features like direction of encirclement or handshake signal timing relationships	Missing essential diagrams, or diagrams that misrepresent system topology (e.g., series instead of parallel connection) or signal timing
Step-by-step derivation	25%	2.5	Complete derivation in (a) from characteristic equation through Euler expansion of e^(-jωT), separation of real/imaginary parts, elimination of K to obtain ω = cot(ωT), and back-substitution for K₀; systematic error formula derivation in (c)	Derivation present but with skipped steps, missing justification for selecting smallest ω₀, or incomplete algebraic manipulation in error propagation	Missing critical derivation steps, jumping to conclusions without showing intermediate working, or incorrect mathematical operations in complex number handling
Practical interpretation	20%	2	Insightful comment on stability margin sensitivity to dead time in (a), practical trade-offs between I/O mapping techniques for 8085-based industrial controllers like those used in Indian power plants, and reasoned judgment on when limiting vs probable error bounds are appropriate for protection relay settings in (c)	Generic comments without specific application context, or superficial treatment of practical implications	Missing critical commentary entirely, or irrelevant practical remarks showing misunderstanding of engineering applications

Q2

Directive word: Compare

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