(a) The open-loop transfer function of a feedback control system incorporating a dead time element is given by: G(s) =…

(a) Stability limit of a loop with dead time

Characteristic equation. With unity feedback, 1 + G(s) = 0 gives s(s + 1) + Ke^(−Ts) = 0

Boundary of stability. On the stability boundary a closed-loop pole lies on the jω-axis. Put s = jω: −ω² + jω + K(cos ωT − j sin ωT) = 0 Real part: K cos ωT = ω² …(1) Imaginary part: K sin ωT = ω …(2) Dividing (1) by (2): cot ωT = ω, that is, ω = cot(ωT) From (2), the gain on the boundary is K = ω/sin(ωT) = ω cosec(ωT)

Why the smallest root is the one that matters. The open-loop phase is ∠G(jω) = −90° − tan⁻¹ω − ωT (in degrees, with ωT converted) It falls monotonically from −90° as ω rises, so it reaches −180° first at the frequency where tan⁻¹ω + ωT = 90°. That condition is tan(ωT) = cot(tan⁻¹ω) = 1/ω, which is ω = cot(ωT). So the smallest positive root ω₀ is the first phase-crossover frequency. The magnitude there is

|G(jω₀)| = K/(ω₀√(1 + ω₀²))

Nyquist argument. G(s) has no open-loop poles in the right half-plane (the pole at the origin is bypassed). The closed loop is therefore stable if the Nyquist plot does not encircle −1, which requires its first crossing of the negative real axis to lie to the right of −1: K/(ω₀√(1 + ω₀²)) < 1 ⇒ K < ω₀√(1 + ω₀²) Since ω₀T = 90° − tan⁻¹ω₀, sin(ω₀T) = cos(tan⁻¹ω₀) = 1/√(1 + ω₀²). So √(1 + ω₀²) = cosec(ω₀T) and K < K₀ = ω₀ cosec(ω₀T) The later crossings (phase −540°, −900°, …) occur at larger ω, where |G| = K/(ω√(1 + ω²)) is smaller still, so they cannot reach −1 if the first crossing does not. Hence, for a given T, the closed loop is stable for all 0 < K < K₀.

Numerical check (T = 1 s). ω = cot ω gives ω₀ = 0.860 rad/s, and K₀ = 0.860 × √(1 + 0.740) = 1.135. With K = 1 the plot crosses at −0.881, so the loop is stable. Other values: T = 0.5 s gives K₀ = 2.15; T = 2 s gives K₀ = 0.61. More dead time lowers the permissible gain. As T → 0, ω₀ → ∞ and K₀ → ∞, which recovers the result that the second-order loop without delay is stable for every K.

(b)(i) I/O-mapped I/O versus memory-mapped I/O in the 8085

• Address space. In I/O-mapped (peripheral-mapped) I/O a port has an 8-bit address, giving 256 input and 256 output ports in a space separate from memory. In memory-mapped I/O a port is given a 16-bit address inside the 64 KB memory map and is treated as a memory location.
• Control signals. In I/O-mapped I/O the CPU makes IO/M̄ = 1, and decoding with RD̄/WR̄ gives IOR̄ and IOW̄. In memory-mapped I/O, IO/M̄ = 0 gives MEMR̄ and MEMW̄.
• Instructions. I/O-mapped ports are reached only by IN port and OUT port (2 bytes, 10 T-states), and data always passes through the accumulator. The 8-bit port address appears on both A7–A0 and A15–A8. Memory-mapped ports can be reached by every memory-reference instruction (MOV r,M, MOV M,r, LDA, STA, LDAX, STAX, ADD M, ANA M, CMP M), with any register, and arithmetic or logic can be done directly on port data.
• Hardware and memory. I/O-mapped I/O needs only 8-bit decoding and leaves the full 64 KB for memory. Memory-mapped I/O needs 16-bit decoding (or partial decoding with fold-back addresses) and reduces the memory space available.
• Typical choice. I/O-mapped I/O suits small systems with few ports. Memory-mapped I/O suits systems that need many ports or flexible data handling.

(b)(ii) Port A modes of the 8255 and handshaking

Modes of Port A (set by the control word, D7 = 1)

• Mode 0, basic I/O. Port A is a simple latched output or an unlatched input port, with no handshake signals.
• Mode 1, strobed I/O. Port A works as input or output with three Port C lines as handshake signals. For input these are PC4 = STB̄_A, PC5 = IBF_A and PC3 = INTR_A. For output they are PC7 = OBF̄_A, PC6 = ACK̄_A and PC3 = INTR_A.
• Mode 2, strobed bidirectional bus. This mode is available only for Port A and uses five lines, PC3–PC7 (INTR, STB̄, IBF, ACK̄, OBF̄). The interrupt-enable flip-flops are set through the BSR mode: PC4 for input (INTE_A) and PC6 for output. For example, the control word B0H sets Port A to mode 1 input and Port B to mode 0 output.

Handshaking. A handshake synchronises a slow or asynchronous peripheral with the CPU, so that a byte is neither lost nor read twice. Each side signals when data is ready and when it has been taken.

Input handshake (mode 1)

1. The peripheral places data on PA0–PA7 and pulses STB̄ low, which latches the data into Port A.
2. IBF goes high, telling the peripheral that the input buffer is full and it must wait.
3. On the rising edge of STB̄, if INTE_A = 1, INTR goes high to interrupt the CPU (or the CPU polls IBF).
4. The CPU reads Port A. The falling edge of RD̄ clears INTR and the rising edge clears IBF, so the peripheral may send the next byte.

Output handshake (mode 1)

1. The CPU writes a byte to Port A. The rising edge of WR̄ clears INTR and drives OBF̄ low, meaning "data ready".
2. The peripheral takes the data and pulses ACK̄ low, which returns OBF̄ high.
3. On the rising edge of ACK̄, if INTE_A = 1, INTR goes high to ask the CPU for the next byte.

(c) Total current with limiting and probable errors

Nominal value: I = I₁ + I₂ = 100 + 200 = 300 A

(i) Limiting error. For a sum, the absolute limiting errors add, which is the worst case with both errors at their extremes and of the same sign: δI = ±(2 + 5) = ±7 A I = 300 ± 7 A (relative limiting error ±2.33%)

(ii) Probable error. Treating ±2 A and ±5 A as probable errors of independent random measurements, they combine as the root sum of squares: r = ±√(2² + 5²) = ±√29 = ±5.39 A I = 300 ± 5.39 A (relative probable error ±1.80%)

Comment. The limiting error is a guaranteed bound: the true value cannot lie outside 293–307 A. It is pessimistic, because it assumes both branch errors are simultaneously at their maxima and add. Independent random errors partly cancel, so the probable error is smaller. About half of repeated results would fall within ±5.39 A. The ±5 A error of I₂ dominates both results, so a more accurate I₂ measurement would improve the total most.