(a) The block diagram of a system is as shown below : Evaluate the overall transfer function $\frac{Y(s)}{R(s)}$ using block diagram reduction technique. 10

(b) Explain the operation performed by 8085 microprocessor when the following instructions a

Question

(a) The block diagram of a system is as shown below : Evaluate the overall transfer function $\frac{Y(s)}{R(s)}$ using block diagram reduction technique. 10

(b) Explain the operation performed by 8085 microprocessor when the following instructions are executed :
(i) JMP unconditionally
(ii) POP
(iii) PUSH
(iv) RET
(v) STC 2×5=10

(c) For the circuit shown in the figure below give expression for the overall uncertainty in the value of combined resistance R. Further, evaluate the overall uncertainty in the value of combined resistance R, when individual values of the resistors are as R₁ = 50 ± 0·1 Ω, R₂ = 100 ± 0·2 Ω, R₃ = 100 ± 0·2 Ω. 10

(d) A factory has a fixed load of 860 kW and is operating at 0·85 power factor. The electric utility company offers to supply energy at the following two alternate rates :
(i) LV supply at ₹ 30/kVA max demand/annum + 12 paise/kWh
(ii) HV supply at ₹ 25/kVA max demand/annum + 10 paise/kWh
The HV switchgear costs ₹ 50/kVA and switchgear losses at full load amount to 4%. Interest and depreciation charges for switchgear are 10% of the capital cost. If the factory is to work 48 hours/week, then determine the more economical tariff option. 10

(e) If the generator polynomial is (x⁴ + x + 1) and the message bits are 1101101, then obtain the CRC code. 10

UPSC Answer Check · Accepted Answer

Evaluate requires systematic analysis with quantitative rigour. Structure: (a) Block diagram reduction (10 marks, ~25% time) – apply Mason's gain formula or successive reduction; (b) 8085 instructions (10 marks, ~20% time) – explain opcode fetch, memory read/write cycles for each; (c) Uncertainty analysis (10 marks, ~20% time) – derive partial derivative formula then substitute values; (d) Tariff economics (10 marks, ~25% time) – calculate annual costs for both options including switchgear economics; (e) CRC generation (10 marks, ~10% time) – perform polynomial division. No conclusion needed; present each part clearly with part-headers.
- Part (a): Correct application of block diagram reduction rules (shifting take-off points, combining blocks in series/parallel, eliminating feedback loops) to obtain Y(s)/R(s)
- Part (b): Accurate description of T-states, memory operations, stack pointer manipulation, and flag effects for all five 8085 instructions (JMP, POP, PUSH, RET, STC)
- Part (c): Derivation of uncertainty propagation formula using partial derivatives for combined resistance, followed by numerical evaluation with given tolerances
- Part (d): Complete economic analysis including kVA demand calculation, annual energy consumption, switchgear capital and running costs, and comparison of LV vs HV tariffs
- Part (e): Correct polynomial long division of message bits by generator polynomial (x⁴+x+1) to obtain 4-bit CRC remainder and final codeword
- Recognition that parts (a), (c), (d), (e) require numerical working while (b) requires descriptive technical depth
- Proper unit handling and significant figure discipline in all calculations
- Cross-verification of results (e.g., checking CRC by polynomial multiplication)

Dimension	Weight	Max marks	Excellent	Average	Poor
Concept correctness	25%	12.5	Demonstrates flawless grasp of control theory fundamentals in (a), 8085 architecture in (b), error propagation theory in (c), power system economics in (d), and cyclic coding theory in (e); no conceptual errors in any sub-part	Shows reasonable understanding of most concepts but minor errors in one sub-part (e.g., incorrect T-state count for 8085, or confusion between absolute and relative uncertainty)	Fundamental misconceptions evident in multiple sub-parts (e.g., treating block diagram reduction as simple algebraic cancellation, or misunderstanding CRC as checksum)
Numerical accuracy	25%	12.5	All calculations precise: correct transfer function coefficients in (a), uncertainty value within rounding tolerance in (c), annual cost comparison accurate to rupees in (d), correct 11-bit CRC codeword in (e)	Correct methodology but arithmetic slips in one calculation (e.g., power factor correction error in tariff calculation, or off-by-one in polynomial degree)	Multiple calculation errors or missing numerical working; order-of-magnitude mistakes in uncertainty or economic analysis
Diagram quality	15%	7.5	Clear redrawn block diagrams for (a) showing each reduction step; timing diagrams for 8085 instructions in (b); circuit diagram for (c) with uncertainty annotations; system layout sketch for (d); polynomial division layout for (e)	Adequate diagrams for (a) and (c) but missing timing diagrams for (b); or diagrams present but poorly labelled	No diagrams despite question references; or diagrams that misrepresent the system structure
Step-by-step derivation	20%	10	Methodical progression visible: each block reduction step shown in (a), T-state sequences enumerated in (b), partial derivative derivation explicit in (c), cost components itemised in (d), XOR operations shown for CRC in (e)	Correct final results but some intermediate steps skipped or compressed; jumps in logic that examiner must infer	Only final answers with no derivation; or incorrect sequence of operations that invalidates results
Practical interpretation	15%	7.5	Contextual insights: comments on stability implications of transfer function in (a), real-world 8085 applications in (b), instrument precision grades in (c), payback period for HV investment in (d), error detection capability of chosen CRC in (e)	Brief mention of practical relevance in one or two parts but mostly theoretical treatment	Purely mechanical solutions with no connection to engineering practice or economic reality

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