(a) The block diagram of a system is as shown below : Evaluate the overall transfer function (Y(s))/(R(s)) using block diagram…

(a) Block diagram reduction. Let E1 be the output of J1 and V2 the output of J2. The H1 path is a negative feedback loop around G1 at J2, so the inner loop reduces to G1/(1+H1). No take-off shifting is needed because H1 and H2 are both taken from the same V2 point; if a take-off were moved across a block, the feedback signal would have to be multiplied by that block. The H2 path returns V2 to J1 with negative sign, so the second loop encloses the reduced block G1/(1+H1). Reducing it gives V2/R = [G1/(1+H1)]/[1+H2G1/(1+H1)] = G1/(1+H1+G1H2). Equivalently, E1=R-H2V2 and V2=G1E1-H1V2, which solves to the same result. The V2 signal then passes through G2 to J3, while R also enters J3 positively through G3. Therefore Y=G2V2+G3R, and Y/R = G1G2/(1+H1+G1H2)+G3 = [G1G2+G3(1+H1+G1H2)]/(1+H1+G1H2).

(b) 8085 instructions. JMP is an unconditional 16-bit jump. It requires 6 T-states: one opcode-fetch cycle, followed by two memory-read cycles that fetch the low and high address bytes, after which PC is loaded with the 16-bit address. No flags are affected. PUSH is a 10 T-state stack instruction. After opcode fetch, it performs two memory-write cycles: SP is decremented and the high-order byte of the register pair is written, then SP is decremented again and the low-order byte is written; for PUSH PSW the accumulator and flag byte are stored. POP is the reverse operation and also takes 10 T-states. It performs two memory-read cycles: the byte at SP is loaded into the low-order register, SP is incremented, the next byte is loaded into the high-order register, and SP is incremented again; POP PSW restores the accumulator and flags. RET is an unconditional return instruction, not a conditional one, and takes 10 T-states. It pops the 16-bit return address from the stack into PC using two memory reads and two SP increments; flags are unchanged. STC is a 6 T-state flag instruction. It sets the carry flag to 1, leaves the other flags unchanged, and involves no memory read or write.

(c) Uncertainty in combined resistance. The circuit is R1 in series with the parallel combination of R2 and R3, so R=R1+R2R3/(R2+R3). Because R is nonlinear in R2 and R3, the partial-derivative method is used. For independent uncertainties, the absolute uncertainty is ΔR=[(∂R/∂R1 ΔR1)²+(∂R/∂R2 ΔR2)²+(∂R/∂R3 ΔR3)²]¹/2. Here ∂R/∂R1=1, ∂R/∂R2=R3²/(R2+R3)², and ∂R/∂R3=R2²/(R2+R3)². Hence ΔR=[(ΔR1)²+(R3²/(R2+R3)² ΔR2)²+(R2²/(R2+R3)² ΔR3)²]¹/2. Substituting R1=50 Ω, R2=R3=100 Ω, ΔR1=0.1 Ω, ΔR2=ΔR3=0.2 Ω gives R=50+100×100/(100+100)=100 Ω. The derivative terms are 1, 0.25 and 0.25, so ΔR=[0.1²+(0.25×0.2)²+(0.25×0.2)²]¹/2=[0.01+0.0025+0.0025]¹/2=0.122 Ω. To the precision justified by the data, R=100±0.12 Ω by root-sum-square. If the tolerances are interpreted as worst-case limits, the bound is 0.1+0.05+0.05=0.20 Ω.

(d) Tariff economics. The maximum demand of the factory is 860/0.85=1011.76 kVA. The annual running hours are 48×52=2496 h, so the annual load energy is 860×2496=2,146,560 kWh. The LV tariff gives an annual demand charge of 30×1011.76=₹30,353 and an energy charge of 12 paise/kWh, i.e. ₹0.12×2,146,560=₹257,587. Total LV cost is therefore ₹287,940 per annum. For HV supply, the switchgear losses are 4% of full load. In apparent power this is 0.04×1011.76=40.47 kVA, and in active power at the same power factor it is 0.04×860=34.4 kW. These losses must be included both in the billed maximum demand and in the energy billed. The billed maximum demand is 1011.76+40.47=1052.24 kVA, so the HV demand charge is 25×1052.24=₹26,306. The billed energy is 2,146,560+34.4×2496=2,232,422 kWh, giving an energy charge of ₹0.10×2,232,422=₹223,242. The switchgear capital cost is 50×1011.76=₹50,588, and 10% interest and depreciation gives an annual charge of ₹5,059. Total HV cost is 26,306+223,242+5,059=₹254,607 per annum. If the switchgear capital is assessed on the billed kVA rather than the load kVA, the annual charge rises only to ₹5,261 and the total to ₹254,809, so the verdict is unchanged. HV supply is therefore more economical by about ₹33,333 per annum.

(e) CRC code. The generator polynomial x⁴+x+1 corresponds to the 5-bit divisor 10011. Since the generator degree is 4, four zeros are appended to the 7-bit message 1101101, giving 11011010000. Binary division is performed by XOR. The first five bits 11011⊕10011=01000; bringing down the next 0 gives 10000. Then 10000⊕10011=00011; bringing down 1 gives 00111. The leading bit is 0, so bring down 0 to get 01110; again the leading bit is 0, so bring down 0 to get 11100. Now 11100⊕10011=01111; bringing down 0 gives 11110. Then 11110⊕10011=01101; bringing down 0 gives 11010. Finally 11010⊕10011=01001. The 4-bit remainder is 1001. The CRC code is the message followed by this remainder: 11011011001. As a check, dividing 11011011001 by 10011 gives remainder 0000, confirming that the codeword is divisible by the generator polynomial. The overall economic verdict is that HV supply is the more economical tariff option.