(a) (i) Sketch the approximate root locus plot for a time-delay system approximated by the transfer function G(s) =…

(a)(i) Root locus of the time-delay (Padé) approximation

Poles and zero. Clearing the fractions:

G(s) = K(1 − s/2)/[s(s + 1)(1 + s/2)] = K(2 − s)/[s(s + 1)(s + 2)]

The poles are s = 0, −1 and −2. The zero is at s = +2, in the right half-plane. This non-minimum-phase zero is how the first-order Padé approximation represents a time delay.

Nature of the locus. Writing G = −K(s − 2)/[s(s + 1)(s + 2)], the characteristic equation for positive K is a 0° (complementary) root locus in the pole–zero form. A real-axis point lies on the locus when an even number of poles and zeros lie to its right. The locus therefore occupies:

• [−1, 0],
• (−∞, −2],
• [2, ∞).

Branches.

• With n − m = 2, two branches go to infinity along asymptotes at 0° and 180°.
• The branch from −2 runs left to −∞.
• The branches from 0 and −1 meet at the breakaway point, where dK/ds = 0 with K = −s(s + 1)(s + 2)/(2 − s). This gives s = −0.378 at K = 0.16.
• They then leave the real axis, cross the jω-axis, and re-enter the real axis at s = +3.42 (K = 57.7).
• After re-entry, one branch ends on the zero at +2 and the other goes to +∞.

Routh test. The characteristic equation is s³ + 3s² + (2 − K)s + 2K = 0.

• s³: 1; 2 − K
• s²: 3; 2K
• s¹: (6 − 5K)/3;
• s⁰: 2K;

Stability requires K strictly between 0 and 6/5, so K_max = 1.2.

Verification from the locus. At K = 1.2 the auxiliary equation is 3s² + 2.4 = 0, giving s = ±j0.894. The computed closed-loop roots at K = 1.2 are −3 and ±j0.894 exactly. This is where the complex branches cross the jω-axis on the plot.

(a)(ii) Signal flow graph: transmission and sensitivity

Graph. The node variables are x₁ to x₅ between R and Y. The forward branches are 1, 2, K₁, 1/[s(s + 2)], 1/s and 1. There is a unity self-loop at x₅, and feedback branches x₃ → x₁ (−1), x₅ → x₃ (−2) and x₅ → x₁ (−1). Write D = s²(s + 2).

Loops.

• L₁ = 2K₁(−1) = −2K₁
• L₂ = (1/D)(−2) = −2/D
• L₃ = −2K₁/D
• L₄ = +1 (the self-loop)

Only L₁ and L₄ do not touch each other.

Mason's gain formula.

Δ = 1 − (L₁ + L₂ + L₃ + L₄) + L₁L₄ = 1 + 2K₁ + 2/D + 2K₁/D − 1 − 2K₁ = 2(1 + K₁)/D

The single forward path is P₁ = 2K₁/D. It touches every loop, so Δ₁ = 1.

T = Y/R = P₁Δ₁/Δ = K₁/(1 + K₁), and the requested transmission is R(s)/Y(s) = (1 + K₁)/K₁.

Node equations confirm this: the unity self-loop forces x₄ = 0, so T is independent of s.

Sensitivity.

S_K₁ = (∂T/∂K₁)(K₁/T) = 1/(1 + K₁)

The sensitivity is the same at s = 10 and at DC (s = 0): 1/(1 + K₁). It is reduced by the loop factor 1 + K₁, which is the benefit of feedback.

For comparison, without the self-loop S = (s³ + 2s² + 2)/[(1 + 2K₁)(s³ + 2s²) + 2(1 + K₁)]. This gives 601/(601 + 1201K₁) at s = 10, but still 1/(1 + K₁) at s = 0.

(b) Hay's bridge: choke coil

Arms.

• Z₁ = R₁ + jωL₁ (AB)
• Z₃ = R₃ (BC)
• Z₄ = R₄′ − j/(ωC₄) (CD), where R₄′ = 70.9 + 0.1 = 71.0 Ω includes the capacitor's series resistance
• Z₂ = R₂ (DA)

Balance condition. Z₁Z₄ = Z₂Z₃:

(R₁ + jωL₁)(R₄′ − j/ωC₄) = R₂R₃

• Imaginary parts: ωL₁R₄′ = R₁/(ωC₄), so R₁ = ω²L₁C₄R₄′.
• Real parts: R₁R₄′ + L₁/C₄ = R₂R₃.

Solving:

L₁ = R₂R₃C₄/(1 + ω²C₄²R₄′²) and R₁ = ω²C₄²R₂R₃R₄′/(1 + ω²C₄²R₄′²)

Numbers.

• ω = 2π × 400 = 2513.3 rad/s
• ωC₄R₄′ = 2513.3 × 0.2 × 10⁻⁶ × 71.0 = 0.03569, so 1 + (0.03569)² = 1.00127
• R₂R₃C₄ = 2000 × 500 × 0.2 × 10⁻⁶ = 0.2

Results.

• L₁ = 0.2/1.00127 = 0.1997 H
• R₁ = (2513.3 × 0.2 × 10⁻⁶)² × 10⁶ × 71.0/1.00127 = 17.92 Ω
• Q = ωL₁/R₁ = 1/(ωC₄R₄′) = 28.0

(Ignoring the 0.1 Ω would give R₁ = 17.89 Ω.)

Phasor diagram (balance, I₁ as reference).

• At balance V_B = V_D, so V_AB = V_AD and V_BC = V_DC.
• V_AB = I₁R₁ + jI₁ωL₁ leads I₁ by θ = tan⁻¹Q = 87.96°. Since V_AD = I₂R₂, I₂ is in phase with V_AB.
• V_BC = I₁R₃ is in phase with I₁. It equals V_DC = I₂R₄′ (along I₂) plus I₂/ωC₄ (lagging I₂ by 90°).
• The supply voltage is V = V_AB + V_BC.

(c) Maskable interrupt and its acknowledge cycle (8085)

Definition. A maskable interrupt is a hardware interrupt that the processor can be told by software to ignore.

• On the 8085, INTR, RST 7.5, RST 6.5 and RST 5.5 are maskable. TRAP is non-maskable.
• EI and DI set and reset the interrupt-enable flip-flop, which enables or disables all maskable interrupts together.
• SIM sets individual mask bits for the RST 7.5/6.5/5.5 inputs, and RIM reads them.

If INTR is active at the end of an instruction and interrupts are enabled, the CPU resets the enable flip-flop and runs an acknowledge sequence instead of the next opcode fetch.

Acknowledge sequence for an RST n response. There are three machine cycles, M1 (6T) + M2 (3T) + M3 (3T):

• M1, INTA cycle (like an opcode fetch):
• T1: ALE is high. Status IO/M̅ = 1, S1 = S0 = 1 identifies an INTA cycle. The PC is placed on the address bus but is not incremented.
• T2: INTA̅ goes low in place of RD̅. The interrupting device puts the RST n opcode on AD₀–AD₇.
• T3: The opcode is latched into the instruction register and INTA̅ returns high.
• T4: The opcode is decoded.
• T5–T6: SP is decremented to prepare the stack push.
• M2, memory write: SP − 1 is on the address bus and the high byte of the PC is written; WR̅ is low in T2–T3.
• M3, memory write: SP − 2 is on the address bus and the low byte of the PC is written.

The PC is then loaded with the vector 8 × n, and the service routine begins.

If the device supplies a CALL opcode instead, M2 and M3 are further INTA̅ cycles that read the two address bytes, followed by two memory-write cycles.