(a) Two generators are connected in parallel to the low-voltage side of a 3-phase, Δ-Y transformer as shown below : Generator 1…

(a)

Choose common base S_base = 90 MVA (transformer rating). Base voltages: LV side 13.8 kV, HV side 69 kV. Base current on LV side: I_base(LV) = S_base / (√3 × V_base(LV)) = 90×10⁶ / (√3 × 13.8×10³) = 3765.33 A.

Generator subtransient reactances on their own bases are both 0.20 pu. Convert to 90 MVA base: X₁ = 0.20 × (90/60) = 0.30 pu. X₂ = 0.20 × (90/30) = 0.60 pu. Transformer reactance Xₜ = 0.10 pu on 90 MVA, 13.8/69 kV.

Pre-fault HV voltage = 66 kV. Since the transformer is unloaded, no voltage drop occurs, so the internal EMF behind each generator subtransient reactance equals this voltage. In per-unit on the 69 kV HV base: V₀ = 66/69 = 22/23 = 0.95652 pu. This is also the per-unit voltage on the LV side because the voltage bases are chosen in the transformer turns ratio.

The two generator subtransient reactances are in parallel, in series with the transformer reactance to the fault. Parallel generator reactance: X_p = (0.30 × 0.60) / (0.30 + 0.60) = 0.18 / 0.90 = 0.20 pu. Total reactance to fault: X_total = X_p + Xₜ = 0.20 + 0.10 = 0.30 pu.

Total subtransient fault current in per-unit: I_f = V₀ / X_total = (22/23) / 0.30 = (22/23) × (10/3) = 220/69 = 3.1884 pu.

The current divides between the parallel generators inversely as their reactances. The voltage across the parallel combination is the same, so: I₁ X₁ = I₂ X₂ ⇒ I₁/I₂ = X₂/X₁ = 0.60/0.30 = 2. Thus I₁ = (2/3) I_f and I₂ = (1/3) I_f.

I₁ = (2/3) × (220/69) = 440/207 = 2.1256 pu. I₂ = (1/3) × (220/69) = 220/207 = 1.0628 pu.

Actual RMS subtransient currents on the LV side: I₁(actual) = 2.1256 × 3765.33 = 8003.6 A. I₂(actual) = 1.0628 × 3765.33 = 4001.8 A.

(b)(i)

Line coding is the process of converting a binary data stream into a discrete-level (digital) voltage or current waveform for baseband transmission. It defines the levels, transitions, DC balance, and clock recovery properties.

Let bit duration be T_b, and use levels +V, −V, 0, with L and H as low and high levels. The data sequence is 1 0 1 0 1 1 1 0.

1. Polar NRZ: 1 = +V, 0 = −V, held for the entire bit. Waveform levels: +V, −V, +V, −V, +V, +V, +V, −V.

2. Bipolar NRZ (AMI): 1 alternates in polarity, 0 = 0 V. First 1 is positive. Ones occur at positions 1, 3, 5, 6, 7. Waveform levels: +V, 0, −V, 0, +V, −V, +V, 0.

3. Differential Manchester: A mid-bit transition always occurs. A start transition represents 0, and no start transition represents 1. Assume the initial level before bit 1 is L. Half-bit pairs for bits 1 to 8: Bit 1 (1): L H Bit 2 (0): L H Bit 3 (1): H L Bit 4 (0): H L Bit 5 (1): L H Bit 6 (1): H L Bit 7 (1): L H Bit 8 (0): L H So the sequence is LH, LH, HL, HL, LH, HL, LH, LH. (The inverted waveform with initial H is equally valid.)

4. RZ polar: 1 = positive for first half and zero for second half; 0 = negative for first half and zero for second half. Half-bit pairs: (+V,0), (−V,0), (+V,0), (−V,0), (+V,0), (+V,0), (+V,0), (−V,0).

(b)(ii)

Number of quantization levels M = 4096. Number of bits per sample: n = log₂ 4096 = 12 bits.

For a full-scale sinusoidal signal in uniform PCM, the maximum signal-to-quantization-noise ratio is: (S/N)_max = 1.76 + 6.02 n dB = 1.76 + 6.02 × 12 = 1.76 + 72.24 = 74.0 dB.

Volume range = 40 dB. The smallest sinusoidal signal is 40 dB below the maximum. Therefore: (S/N)_min = 74.0 − 40 = 34.0 dB.

With 10 dB compression, the effective dynamic range at the quantizer is reduced by 10 dB, i.e., from 40 dB to 30 dB. Hence the new minimum SNR is: (S/N)_min(new) = 74.0 − 30 = 44.0 dB. The maximum SNR stays at about 74.0 dB in this idealised model; in practice the companding penalty lowers it slightly.

(c)

Static differential protection relay using a rectifier bridge amplitude comparator:

Schematic: current transformers CT₁ and CT₂ are placed on the two sides of the protected equipment (transformer, generator or busbar) and connected in the Merz-Price circulating-current arrangement. Two quantities are derived from the CT secondaries:

• Operating (differential) quantity: the spill current I_d = I₁ − I₂ (phasor difference), taken from the equipotential points of the pilot loop through an auxiliary transformer.
• Restraining (bias) quantity: the through current I_r = (I₁ + I₂)/2, taken through a centre-tapped bias transformer in the pilot loop.

Circuit: each quantity is fed to its own full-wave rectifier bridge. Bridge BR_op gives a DC voltage V_op ∝ |I_d| and bridge BR_r gives V_r ∝ k|I_r|, where k is the percentage-bias setting. The two bridge outputs are connected in opposition (circulating-current comparator) across a static level detector (transistor or op-amp comparator) that fires a thyristor to energise the trip coil. Capacitors smooth the rectified outputs, and a setting resistor fixes the minimum pick-up.

Normal load or external (through) fault: I₁ ≈ I₂ and in phase, so I_d ≈ 0 (only CT mismatch error) while I_r is large. V_r > V_op, the net comparator input has restraining polarity, and the relay does not operate.

Internal fault: both sides feed the fault, so the phasor difference I_d becomes large (with infeed from both ends it approaches the total fault current) and exceeds k|I_r|. V_op > V_r, the level detector switches, the thyristor fires, the trip coil is energised and the circuit breaker opens.

Because the magnitudes compared are those of the phasor difference and the phasor sum, phase information is retained; comparing |I₁| with |I₂| alone would fail for an internal fault fed equally from both ends. The percentage-bias characteristic (|I_d| > k|I_r| plus a small minimum setting) keeps the relay stable on heavy through faults with CT saturation or tap mismatch, yet sensitive to internal faults. Being static, the relay has no moving parts, low CT burden, fast operation (about one cycle) and high reliability.